Abstract: The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.

Abstract: An ultraviolet light-emitting diode includes a transparent substrate and an ultraviolet illuminant epitaxial structure. The ultraviolet illuminant epitaxial structure includes an N-type semiconductor layer which is disposed on the transparent substrate and comprised of a first portion and a second portion. The first portion of the N-type semiconductor layer includes a light-emitting layer disposed thereon, a P-type semiconductor layer on the light emitting layer, and a P-type contact layer disposed on the P-type semiconductor layer. The second portion of the N-type semiconductor layer includes an N-type semiconductor film disposed thereon and separated from the light-emitting layer. A band gap of the N-type semiconductor film is smaller than a band gap of the light-emitting layer. The N-type contact is disposed on the N-type semiconductor film. The P-type contact is disposed on the P-type contact layer.

Abstract: An UV light-emitting diode includes a patterned substrate, a template layer, a growth layer, a first n-type semiconductor layer, an intrinsic semiconductor layer, a second n-type semiconductor layer, a plurality of layers of multiple quantum wells, a barrier layer, a first electron blocking layer, a second electron blocking layer, a first p-type semiconductor layer and a second p-type semiconductor layer in sequence from a bottom layer to a top layer. Whereas the aforementioned layers all include Group III nitride materials and the number of layers for the plurality of layers of multiple quantum wells is at least five layers. Because the first n-type semiconductor layer, the first p-type semiconductor layer, and the plurality of layers of multiple quantum wells all contain aluminum, short-wavelength UV light is emitted when a current is applied.

Abstract: An UV light-emitting diode includes a patterned substrate, a template layer, a growth layer, a first n-type semiconductor layer, an intrinsic semiconductor layer, a second n-type semiconductor layer, a plurality of layers of multiple quantum wells, a barrier layer, a first electron blocking layer, a second electron blocking layer, a first p-type semiconductor layer and a second p-type semiconductor layer in sequence from a bottom layer to a top layer. Whereas the aforementioned layers all include Group III nitride materials and the number of layers for the plurality of layers of multiple quantum wells is at least five layers. Because the first n-type semiconductor layer, the first p-type semiconductor layer, and the plurality of layers of multiple quantum wells all contain aluminum, short-wavelength UV light is emitted when a current is applied.

Abstract: A growth method of aluminum gallium nitride is disclosed. The method includes the steps of: providing a substrate; forming a first aluminum gallium nitride layer on the substrate at a first temperature; and forming a second aluminum gallium nitride layer, on the first aluminum gallium nitride layer, at a second temperature. The first temperature is higher than the second temperature.

Abstract: The present application provides a growth method of aluminum nitride (AlN), including the following steps: providing a substrate; using a metal organic chemical vapor deposition (MOCVD) device to simultaneously supply metal source gas, nitrogen source gas and group VI element source gas to the substrate to form an AlN nucleation layer on the substrate; and using the MOCVD device to simultaneously supply the nitrogen source gas and the metal source gas to the AlN nucleation layer to form an AlN crystalline layer on the AlN nucleation layer.

Abstract: A growth method of aluminum gallium nitride is disclosed. The method includes the steps of: providing a substrate; forming a first aluminum gallium nitride layer on the substrate at a first temperature; and forming a second aluminum gallium nitride layer, on the first aluminum gallium nitride layer, at a second temperature. The first temperature is higher than the second temperature.

Abstract: A sapphire substrate with patterned structure includes a sapphire base; a plurality of the cavities formed on a surface of the sapphire base; and a template layer. The plurality of the cavities are periodically arranged at a predetermined distance from each other, and each of the plurality of the cavities has a bottom surface and a top opening. Each of the plurality of the cavities comprises at least a first and a second inclined surfaces, and the first and the second inclined surfaces are inclined by a first and a second angles respectively with respect to the bottom surface of the plurality of the cavities.

Abstract: A method for growing Group III nitride is provided, which includes the following steps. A plurality of notches separated from each other are formed at the epitaxial substrate surface via the pattering process. The plurality of notches each has at least one stepping structure with a predetermined inclination angle, wherein the stepping structure in each notch gradually descends towards the center of the corresponding notch. The Group III nitride is grown on the epitaxial substrate via epitaxy process. Wherein, the Group III nitride growing at an upper portion of the epitaxial substrate restricts the vertical growth of the Group III nitride growing at the lower portion of the epitaxial substrate, and the Group III nitride growing at the lower portion of the epitaxial substrate promotes the lateral growth of the Group III nitride growing at the upper portion of the epitaxial substrate.

Abstract: A sapphire substrate with patterned structure includes a sapphire base; a plurality of the cavities formed on a surface of the sapphire base; and a template layer. The plurality of the cavities are periodically arranged at a predetermined distance from each other, and each of the plurality of the cavities has a bottom surface and a top opening. Each of the plurality of the cavities comprises at least a first and a second inclined surfaces, and the first and the second inclined surfaces are inclined by a first and a second angles respectively with respect to the bottom surface of the plurality of the cavities.

Abstract: A vertical light emitting diode (VLED) die includes a p-type confinement layer, an active layer on the p-type confinement layer configured to emit light, and an n-type confinement structure having at least one etch stop layer configured to protect the active layer. A method for fabricating a vertical light emitting diode (VLED) die includes the steps of: providing a carrier substrate; forming an n-type confinement structure on the carrier substrate having at least one etch stop layer; forming an active layer on the n-type confinement structure; forming a p-type confinement layer on the active layer; and removing the carrier substrate.