Abstract: An apparatus for updating firmware or parameters is disclosed. The apparatus is disposed in a computer system and electrically coupled to a platform controller hub (PCH) chipset having a first USB host interface and a nonvolatile memory. The apparatus comprises: a second USB host interface; a switch element, electrically coupled to the first USB host interface, the second USB host interface and a USB device, wherein the switch element electrically couples the USB device to either the first USB host interface or the second USB host interface; and a control element, electrically coupled to the second USB host interface and the switch element, wherein when the computer system is not powered on normally, the control element controls the switch element to electrically couple the USB device to the second USB host interface, wherein the control element fetches a firmware or parameters stored in the USB device and updates the nonvolatile memory with the fetched firmware or the parameters.

Abstract: A bridge system includes a request device, connected to a first bus; a target device, connected to a second bus; and a bridge, communicated with the first bus and the second bus, and the bridge has a buffer, wherein when the request device asks the bridge for reading data of a target address from the target device, a transaction is started, and the bridge asks the target device to transfer data of the target address and following addresses, and then the target device retrieves and transfers the data of the target address and following addresses to the bridge, that is stored in the buffer and then transferred to the request device in turn, and wherein as amount of transferred data to the request device reaches a threshold, the bridge continuously asks data of a following address of the target device before the transaction is finished.

Abstract: A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signal is transmitted on a clock pin and a data signal is transmitted on a data pin. In each of the suspending intervals, the clock signal stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using a plurality of registers. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of the integrated circuit.

Abstract: An integrated storage device and a control method thereof are provided. The integrated storage device includes an interface controller, a microcontroller, a plurality of non-volatile storage devices, and a channel link controller. The interface controller retrieves a master control signal and a slave control signal sent by a motherboard. The microcontroller generates a selecting signal. The non-volatile storage devices have at least two storage types. The non-volatile storage devices are divided into a first group of storage device and a second group of storage device according to the selecting signal. The channel link controller respectively controls the first group of storage device and the second group of storage device according to the master control signal and the slave control signal. Thereby, the accessing efficiency of the integrated storage device is increased.

Abstract: A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signals is transmitted on a clock pin and a data signals is transmitted on a data pin. In each of the suspending intervals, the clock signals stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using any register. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of integrated circuit.

Abstract: A data processing apparatus for loop structure is provided. The apparatus includes a fast memory device and a loop detector. The loop detector is coupled to a processor to detect whether the processor performs a loop structure or not. When the processor performs the loop structure, the loop detector outputs a control signal. According to the control signal, the apparatus stores a loop structure data corresponding to the loop structure in the fast memory device for the processor to perform the loop structure.

Abstract: A data processing apparatus for loop structure is provided. The apparatus includes a fast memory device and a loop detector. The loop detector is coupled to a processor to detect whether the processor performs a loop structure or not. When the processor performs the loop structure, the loop detector outputs a control signal. According to the control signal, the apparatus stores a loop structure data corresponding to the loop structure in the fast memory device for the processor to perform the loop structure.