Abstract: A method of forming a bottom storage node of a DRAM capacitor over a contact plug is disclosed. The method comprises the steps of: depositing an oxide layer over the contact plug; etching the oxide layer using a first photoresist layer having with a first masking pattern, the first masking pattern allowing the removal of the oxide layer over the contact plug; depositing a polysilicon layer over the oxide layer and in electrical contact with the contact plug; forming a second photoresist layer having a second masking pattern onto the polysilicon layer, the second masking pattern being substantially similar to the first masking pattern, but rotated by a predetermined angle; and etching the polysilicon layer in accordance with the second photoresist layer until the oxide layer is reached.

Abstract: A method for fabricating landing pads for DRAM cells is disclosed. The method comprises following steps: At first, a substrate formed with isolation regions, periphery transistor region and a defined DRAM region are patterned so that an oxide layer on the defined DRAM region are removed to expose the source/drain region nitride caps, and nitride spacers. After a polysilicon layer is formed on all resulting surfaces, a photoresist pattern is subsequently formed on the polysilicon layer of the DRAM region so that the photoresist openings over the nitride cap are formed. Next, a conformal polymer layer of about 0.1 .mu.m in thickness is formed on all resulting surfaces so that a smaller polymer opening about 0.1 .mu.m size or beyond is formed in each of the photoresist openings. Finally, using the polymer layer as a mask and the nitride cap as a stopping layer, a polymer etching and a polysilicon etching are performed so that the landing pads are generated.

Abstract: The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.

Abstract: A method is disclosed for forming Y-shaped holes in semiconductor substrates by using Y-contact etching. The hole is formed with a single, two-step dry-etching process in a single chamber with one masking step for the whole hole. The upper portion of the Y-shaped hole is formed by means of an isotropic tapered dry-etching process while the lower portion is formed by means of a straight anisotropic recipe of the same dry-etching process. The result is a Y-shaped hole formed with fewer process steps and with maximized contact area for improved reliability.

Abstract: A method for forming a metal interconnect structure over a high topography dielectric is disclosed. The method comprises the steps of: depositing a conductive layer over the high topography dielectric layer; depositing a planarized oxide layer over the conducting layer, patterning and etching the planarized oxide layer in accordance with a desired metal interconnect pattern using the conducting layer as an etching stop; using the planarized oxide layer as a hard mask, etching the conducting layer in accordance with the desired metal interconnect pattern imparted onto the planarized oxide layer; and depositing a gap-filling oxide layer over the planarized oxide layer and the high topography dielectric layer.

Abstract: An integrated circuit (IC) fabrication method is provided for the fabrication of an electrode structure having an increased surface area for a double-crown type of capacitor in a dynamic random-access memory (DRAM) device. In this method, damascene technology is used, which can help reduce the height difference between the memory cell region and the peripheral region, thus eliminating the required planarization process in the prior art. Moreover, this method can provide an electrode structure having a large surface area that allows the associated capacitor to be considerably increased in capacitance as compared to the prior art while requiring no increase in the layout area in the integrated circuit.

Abstract: A method for manufacturing an 8-shaped bottom storage node. A dielectric layer and a polysilicon layer are deposited. A bit line contact and a storage node contact are formed through the dielectric layer and the polysilicon layer down to an access transistor. After formation of the bit line contact and the storage node contact, the polysilicon layer is removed leaving the first dielectric layer. A polysilicon layer is deposited over the dielectric layer and into the bit line contact and storage node contacts. This is followed by a deposition of a tungsten silicide layer and a second dielectric layer. These layers are then etched to form a bit line above the bit line contact. Sidewall spacers are formed on the sidewalls of the bit line. Another polysilicon layer is deposited into the storage node contacts and above the bit line. This polysilicon layer is patterned and etched in an 8 pattern. Oxide spacers are formed on the sidewalls of the etched polysilicon layer.

Abstract: A method for forming a DRAM cell of a DRAM circuit is disclosed. The DRAM circuit includes a periphery region and a cell region. The DRAM cell is in the cell region and comprises an access transistor and a capacitor. The access transistor has a gate, a source, and a drain. The periphery region includes a plurality of gates. The method comprises the deposition of a silicon oxynitride layer over the gates, the silicon oxynitride layer acting as a bottom anti-reflection coating. That portion of the silicon oxynitride layer that lies over the DRAM cell is removed. A landing pad is formed over the source of the access transistor and a bitline pad is formed over the drain of the transistor. Next, a first oxide layer is formed over the landing pad and the bitline pad. A capacitor is formed over the landing pad and a second oxide layer is formed over the capacitor.

Abstract: A method is disclosed for forming Y-shaped holes in semiconductor substrates by using Y-contact etching. The hole is formed with a single, two-step dry-etching process in a single chamber with one masking step for the whole hole. The upper portion of the Y-shaped hole is formed by means of an isotropic tapered dry-etching process while the lower portion is formed by means of a straight anisotropic recipe of the same dry-etching process. The result is a Y-shaped hole formed with fewer process steps and with maximized contact area for improved reliability.

Abstract: A method for forming a patterned polysilicon layer employed within an integrated circuit structure. There is first provided a semiconductor substrate having formed thereupon a topographic substrate layer. There is then formed over the semiconductor substrate including the topographic substrate layer a polysilicon layer. There is then formed over the polysilicon layer an etch mask layer. There is then etched the polysilicon layer within a first reactive ion etch (RIE) plasma employing a first etchant gas composition which comprises a chlorine containing etchant species to form a patterned polysilicon layer and a patterned polysilicon containing layer residue. Finally, there is then over-etched the patterned polysilicon layer and the patterned polysilicon containing layer residue within a second reactive ion etch (RIE) plasma employing a second etchant gas composition which comprises an oxygen containing etchant species and a bromine containing etchant species.

Abstract: A new method for forming a feature having a feature size of one half the resolution of the photolithography process by adjusting the etching conditions is achieved. A capping oxide layer is deposited overlying the feature layer. A first layer of photoresist is patterned using a photolithography process to provide a first photomask having a first feature size. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a first oxide mask having a second feature size one half the width of the first feature size. The first photomask is removed. A second photoresist layer is patterned to provide a second photomask for forming the second feature wherein the second photomask has a first feature size and is shifted horizontally by twice the desired feature size from the first photomask.

Abstract: Voids in via holes in integrated circuits have been effectively removed by heating the vias to a relatively low temperature and then subjecting the entire structure (including the vias) to artificial gravitational forces. Said forces may be steadily applied, as in centrifuging, or they may be applied intermittently by using a jerking motion which is repeated several times. A number of different ways for implementing such jerking motion are described. These include magnetic repulsion, vertical pulling by a motor, and providing a pressure differential between the top and bottom sides of the integrated circuit holder.

Abstract: The time needed to planarize the surface of an integrated circuit is reduced by causing the planarization liquid to settle in the presence of artificial gravity that supplements natural gravity. A number of different ways to achieve artificial gravity are described. These include centrifuging, magnetic repulsion, vertical pulling by a motor, and providing a pressure differential between the top and bottom sides of the wafer holder.

Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer formed from an organic anti-reflective coating (ARC) material, where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing a reactant gas composition comprising trifluoromethane, carbon tetrafluoride, oxygen and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer.

Abstract: A method for manufacturing an array of double-crown-shaped storage capacitors with increased capacitance on a dynamic random access memory (DRAM) device has been achieved. The invention utilizes a polysilicon and silicon nitride spacer to form the double-crown capacitors while forming concurrently bit lines and node contacts for the bottom electrodes of the storage capacitors. A silicon nitride layer and a silicon nitride spacer are used to insulate the bit lines from the capacitors formed thereon. The polysilicon sidewall spacer is used to pattern a very narrow vertical insulating structure on which is formed the polysilicon double crown by depositing another polysilicon layer which is etched back. The vertical insulating structures are removed by selective etching leaving a free-standing bottom electrode having a double-crown-shaped structure. An interelectrode dielectric layer having a high dielectric constant, and a final polysilicon layer are deposited to complete the storage capacitors for the DRAM.