Abstract: A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench.

Abstract: A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench.

Abstract: A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench.

Abstract: A memory device includes a substrate, a first digit line, a first capacitor and a metal shield. The substrate has a plurality of active areas and an isolation area. The first digit line and the first capacitor are connected to a first active area of the active areas. The second digit line is connected to a second active area of the active areas. The metal shield is located on the insolation area and between the first digit line and the second digit line. The metal shield is electrically insulated with the first digit line and the second digit line.

Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.

Abstract: The present disclosure provides a test system, and a method of operating the same. The test system is for testing a DRAM (dynamic random access memory). The DRAM includes an array including a first memory row and a second memory row. The first memory row includes a first word line. The second memory row includes a second word line and a test cell. The second word line is immediately adjacent to the first word line. The test cell is controllable by the second word line. The test system includes a work station. The work station is configured to evaluate a row hammer effect on the second memory row based on a leakage charge, caused by an AC component of a pulse applied to the first word line, from the test cell.

Abstract: The present disclosure provides a test system, and a method of operating the same. The test system is for testing a DRAM (dynamic random access memory). The DRAM includes an array including a first memory row and a second memory row. The first memory row includes a first word line. The second memory row includes a second word line and a test cell. The second word line is immediately adjacent to the first word line. The test cell is controllable by the second word line. The test system includes a work station. The work station is configured to evaluate a row hammer effect on the second memory row based on a leakage charge, caused by an AC component of a pulse applied to the first word line, from the test cell.

Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.

Abstract: A functionless transistor device includes a semiconductor substrate, a channel, a first source/drain, a second source/drain, a gate and a gate dielectric layer. The channel includes a first channel extending in a lateral direction, and a second channel extending in a vertical direction. The first source/drain is in contact with the first channel. The second source/drain is in contact with the second channel. The channel, the first source/drain and the second source/drain have the same doping type. The gate is disposed over an upper surface of the first channel and side surfaces of the second channel, and the gate has a second doping type opposite to the first doping type. The gate dielectric layer is disposed between the gate and the channel.

Abstract: A method for fabricating a semiconductor device with high-k materials. A high-k dielectric layer is formed on a substrate, followed by a fluorine-containing treatment of the high-k dielectric layer, forming an interface containing Si—F bonds.