Abstract: A time-division (TD) decimation filter bank includes two decimation filter units. The first decimation filter unit operates at a system clock and receives a first-stage input data string. Each data in the first-stage input data string has a first part data and second part data. During the odd clock periods, the first part data are filtered and decimated in frequency. During the even clock periods, the second part data are filtered and decimated in frequency. The second decimation filter unit operates at the system clock and 2N clock periods are set as an operation-period unit, N?2. The second decimation filter unit receives the outputs from the first decimation filter unit and receives several feedback data of the second decimation filter unit by TD, so that the received data are distributed into the 2N clock periods for filtering and decimation and outputting by TD.

Abstract: A method for timing error detection decision lock includes the following steps. Multiple detected values are obtained from a transmission signal. A moving sum mean signal is obtained according to the detected values. The moving sum mean signal is sampled every second constant period to obtain multiple sampling values. Whether the transmission signal is in a timing-lock status or an un-timing-lock status is determined according to relative relationships between the sampling values.

Abstract: An automatic gain control method includes receiving a sequence of multiple digital data, and calculating a plurality of signal values corresponding to the respective voltage values of the digital data, such as multiple peak-to-peak voltage values or power values, so as to optimize a gain according to variations in the output values. The gain optimization includes updating a reference value according to the signal values. If the reference value is less than a minimum threshold, the gain is increased to cause the reference value to reach the minimum threshold. The gain optimization also includes analyzing a clipping rate according to the signal values. If the clipping rate is equal to zero, then the gain is adjusted up. If the clipping rate is greater than zero, then the gain is adjusted down, such that the clipping rate is decreased to approach to zero.

Abstract: A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result.

Abstract: A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.

Abstract: A method for spectrum noise detection is provided. Means and a total mean of spectrum blocks of a frequency-domain signal are calculated. Whether the means are greater than a cut-off threshold is checked. If all the means are greater than the cut-off threshold, whether the means range between a variance lower bound and a variance upper bound is checked, an estimation bandwidth corresponding to the spectrum blocks is obtained according to a bandwidth check threshold, and whether a central frequency of the estimation bandwidth approximates a central frequency of the spectrum of the frequency-domain signal is checked. If the number of the means ranging between the variance lower bound and the variance upper bound exceeds a default value, and the estimation bandwidth is greater than a predetermined bandwidth and the central frequency of the estimation bandwidth approximates the central frequency, the frequency-domain signal is determined as a noise signal.

Abstract: An automatic gain control method includes receiving a sequence of multiple digital data, and calculating a plurality of signal values corresponding to the respective voltage values of the digital data, such as multiple peak-to-peak voltage values or power values, so as to optimize a gain according to variations in the output values. The gain optimization includes updating a reference value according to the signal values. If the reference value is less than a minimum threshold, the gain is increased to cause the reference value to reach the minimum threshold. The gain optimization also includes analyzing a clipping rate according to the signal values. If the clipping rate is equal to zero, then the gain is adjusted up. If the clipping rate is greater than zero, then the gain is adjusted down, such that the clipping rate is decreased to approach to zero.

Abstract: A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result.

Abstract: A time-division (TD) decimation filter bank includes two decimation filter units. The first decimation filter unit operates at a system clock and receives a first-stage input data string. Each data in the first-stage input data string has a first part data and second part data. During the odd clock periods, the first part data are filtered and decimated in frequency. During the even clock periods, the second part data are filtered and decimated in frequency. The second decimation filter unit operates at the system clock and 2N clock periods are set as an operation-period unit, N?2. The second decimation filter unit receives the outputs from the first decimation filter unit and receives several feedback data of the second decimation filter unit by TD, so that the received data are distributed into the 2N clock periods for filtering and decimation and outputting by TD.

Abstract: A method for spectrum noise detection is provided. Means and a total mean of spectrum blocks of a frequency-domain signal are calculated. Whether the means are greater than a cut-off threshold is checked. If all the means are greater than the cut-off threshold, whether the means range between a variance lower bound and a variance upper bound is checked, an estimation bandwidth corresponding to the spectrum blocks is obtained according to a bandwidth check threshold, and whether a central frequency of the estimation bandwidth approximates a central frequency of the spectrum of the frequency-domain signal is checked. If the number of the means ranging between the variance lower bound and the variance upper bound exceeds a default value, and the estimation bandwidth is greater than a predetermined bandwidth and the central frequency of the estimation bandwidth approximates the central frequency, the frequency-domain signal is determined as a noise signal.

Abstract: A method for timing error detection decision lock includes the following steps. Multiple detected values are obtained from a transmission signal. A moving sum mean signal is obtained according to the detected values. The moving sum mean signal is sampled every second constant period to obtain multiple sampling values. Whether the transmission signal is in a timing-lock status or an un-timing-lock status is determined according to relative relationships between the sampling values.

Abstract: A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.