Patents by Inventor KUNG-WEI LEE
KUNG-WEI LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096884Abstract: A method of making a semiconductor device includes forming a first polysilicon structure over a first portion of a substrate. The method further includes forming a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. The method further includes forming a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, and a difference between the first thickness and the second thickness is at most 10% of the second thickness.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Yu-Shao CHENG, Chui-Ya PENG, Kung-Wei LEE, Shin-Yeu TSAI
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Patent number: 11855086Abstract: A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.Type: GrantFiled: March 18, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Shao Cheng, Chui-Ya Peng, Kung-Wei Lee, Shin-Yeu Tsai
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Publication number: 20210225840Abstract: A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.Type: ApplicationFiled: March 18, 2021Publication date: July 22, 2021Inventors: Yu-Shao CHENG, Chui-Ya PENG, Kung-Wei LEE, Shin-Yeu TSAI
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Patent number: 10957697Abstract: A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.Type: GrantFiled: August 13, 2018Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Shao Cheng, Shin-Yeu Tsai, Chui-Ya Peng, Kung-Wei Lee
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Publication number: 20190006359Abstract: A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.Type: ApplicationFiled: August 13, 2018Publication date: January 3, 2019Inventors: Yu-Shao CHENG, Shin-Yeu TSAI, Chui-Ya PENG, Kung-Wei LEE
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Patent number: 10050035Abstract: A method includes forming a first polysilicon structure over a first portion of a substrate. A second polysilicon structure is formed over a second portion of the substrate. Two spacers are formed on opposite sidewalls of the second polysilicon structure. A layer of protective material is formed to cover the first and second portions of the substrate. The layer of protective material has a first thickness over the second polysilicon structure and a second thickness over the two spacers. The first thickness is equal to or greater than 500 ?, and the second thickness is equal to or less than 110% of the first thickness. A patterned photo resist layer is formed to cover a first portion of the layer of protective material that covers the first portion of the substrate. The second portion of the layer of protective material is removed.Type: GrantFiled: January 17, 2014Date of Patent: August 14, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Shao Cheng, Shin-Yeu Tsai, Chui-Ya Peng, Kung-Wei Lee
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Patent number: 10014207Abstract: A method of filling a dielectric trench includes forming two adjacent conductors on a substrate, forming a dielectric layer over a surface of the conductors and the substrate, removing a portion of the dielectric layer, treating a top surface of the dielectric layer with phosphorous plasma, and repeating the forming the dielectric layer, the removing the portion of the dielectric layer, and the treating the top surface of the dielectric layer in a multi cycle fashion. A narrowest width of the dielectric trench between the two adjacent conductors is smaller than about 30 nm.Type: GrantFiled: July 30, 2015Date of Patent: July 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jia-You Tsai, Kung-Wei Lee
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Patent number: 9589969Abstract: Semiconductor devices and manufacturing methods of the same are disclosed. The semiconductor device includes a die, a conductive structure, a bonding pad and a passivation layer. The conductive structure is over and electrically connected to the die. The bonding pad is over and electrically connected to the conductive structure. The passivation layer is over the bonding pad, wherein the passivation layer includes a nitride-based layer with a refractive index of about 2.16 to 2.18.Type: GrantFiled: January 15, 2016Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wei Chang, Austin Hsu, Kung-Wei Lee, Chui-Ya Peng
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Publication number: 20150340276Abstract: A method of filling a dielectric trench includes forming two adjacent conductors on a substrate, forming a dielectric layer over a surface of the conductors and the substrate, removing a portion of the dielectric layer, treating a top surface of the dielectric layer with phosphorous plasma, and repeating the forming the dielectric layer, the removing the portion of the dielectric layer, and the treating the top surface of the dielectric layer in a multi cycle fashion. A narrowest width of the dielectric trench between the two adjacent conductors is smaller than about 30 nm.Type: ApplicationFiled: July 30, 2015Publication date: November 26, 2015Inventors: JIA-YOU TSAI, KUNG-WEI LEE
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Publication number: 20150206879Abstract: A method includes forming a first polysilicon structure over a first portion of a substrate. A second polysilicon structure is formed over a second portion of the substrate. Two spacers are formed on opposite sidewalls of the second polysilicon structure. A layer of protective material is formed to cover the first and second portions of the substrate. The layer of protective material has a first thickness over the second polysilicon structure and a second thickness over the two spacers. The first thickness is equal to or greater than 500 ?, and the second thickness is equal to or less than 110% of the first thickness. A patterned photo resist layer is formed to cover a first portion of the layer of protective material that covers the first portion of the substrate. The second portion of the layer of protective material is removed.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Shao CHENG, Shin-Yeu TSAI, Chui-Ya PENG, Kung-Wei LEE
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Publication number: 20150048477Abstract: A semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface. The dielectric material includes an aspect ratio substantially equal to or greater than a predetermined value.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: JIA-YOU TSAI, KUNG-WEI LEE