Abstract: An electro-optical device includes a driving transistor in which a source, a light emission control transistor in which the source is connected to a drain of the driving transistor, an OLED element in which one end is connected to the drain of the light emission control transistor, and a first holding capacitor in which one end is connected to a gate of the driving transistor, the other end is connected to the drain of the driving transistor, and holds a potential that corresponds to a potential of a data signal of a designated tone, in which a driving circuit is provided with a non-light emission period of the OLED element per predetermined period in one vertical scanning period, and monotonically decreases a proportion of the non-light emission period in the predetermined period by controlling the light emission control transistor.

Abstract: An electro-optical device includes a driving transistor in which a source, a light emission control transistor in which the source is connected to a drain of the driving transistor, an OLED element in which one end is connected to the drain of the light emission control transistor, and a first holding capacitor in which one end is connected to a gate of the driving transistor, the other end is connected to the drain of the driving transistor, and holds a potential that corresponds to a potential of a data signal of a designated tone, in which a driving circuit is provided with a non-light emission period of the OLED element per predetermined period in one vertical scanning period, and monotonically decreases a proportion of the non-light emission period in the predetermined period by controlling the light emission control transistor.

Abstract: A shift register includes first type D latches in the odd-numbered stage and second type D latches in the even-numbered stage. A pass gate of the first type D latch and a memory controller of the second type D latch are made from a first conductivity type transistor, and a memory controller of the first type D latch and a pass gate of the second type D latch are made from a second conductivity type transistor.

Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: Disclosed is an IC chip using a glass substrate capable of being manufactured at a lower cost than the IC chip using from a semiconductor wafer. Further, where the body substrate of a display device is made of glass, the IC chip and the body substrate can have equal coefficients of thermal expansion, thus preventing the IC chips from peeling off and reducing the failure rate. Furthermore, the gate line driving IC applied to a display device can be arranged as an IC chip having a length approximately equal to the display area, therefore, mounting a plurality of IC chips as the gate driving IC is not required, thereby reducing the production cost. Still further, all gate lines can be extended in parallel from the IC chip so that no difference in the delay occurs among the gate lines and the size of frame of display device can reduced.

Abstract: A driving circuit of an LCD display apparatus, which adjusts the sampling timing of a video signal. Driving signals from a driving IC and a reference power source are supplied via a flexible printed circuit FPC to an LCD panel. A horizontal clock signal is subjected to switching adjustment in a propagation delay adjustment circuit, which alternatively switches a delay amount of the horizontal clock signal between two levels, and the resulting horizontal clock signal subjected to the switching adjustment is then supplied to a horizontal shift register. The FPC generates a switching signal by branching from either a high potential voltage signal VDD or a low potential voltage signal VSS and supplies the switching signal to the propagation delay adjustment circuit. A phase switching circuit having a function similar to that of the propagation delay adjustment circuit may be provided within the driving IC.

Abstract: When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.

Abstract: Disclosed is an IC chip using a glass substrate capable of being manufactured at a lower cost than the IC chip using from a semiconductor wafer. Further, where the body substrate of a display device is made of glass, the IC chip and the body substrate can have equal coefficients of thermal expansion, thus preventing the IC chips from peeling off and reducing the failure rate. Furthermore, the gate line driving IC applied to a display device can be arranged as an IC chip having a length approximately equal to the display area, therefore, mounting a plurality of IC chips as the gate driving IC is not required, thereby reducing the production cost. Still further, all gate lines can be extended in parallel from the IC chip so that no difference in the delay occurs among the gate lines and the size of frame of display device can reduced.