Patents by Inventor Kunia AIHARA

Kunia AIHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9554455
    Abstract: Systems, methods and apparatuses involving a chip-to-chip communication channel, for reducing Far End Crosstalk (FEXT) through the novel concept of controlling FEXT magnitude and polarity of a component inside a channel, vias or within a connector by implementing broadside and edge couplings to offset cumulative FEXT in a channel, via-connector-via subsystem or a connector. The example implementations described herein can be applied to a chip-to-chip communication channel, mezzanine connectors, backplane connectors and any other connectors requiring via routing, and connector itself that can benefit from FEXT reduction.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 24, 2017
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Kunia Aihara, Ching-Chao Huang
  • Patent number: 9257779
    Abstract: An intermediate connection electrical connector includes a plurality of blades and a supporting member for supporting the blades arranged in an arrangement direction. The supporting member includes a surrounding wall portion for surrounding the blades and a regulating portion for positioning the blades. The surrounding wall portion includes a side wall portion and an edge wall portion. The side wall portion is at least partially formed of an electromagnetic wave absorbing material. The regulating portion is disposed inside the surrounding wall portion to define a blade accommodating space for accommodating the blades.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: February 9, 2016
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Nobuhiro Tamai, Toshiyuki Takada, Kunia Aihara, Jeremy Huang, Masakazu Nagata
  • Publication number: 20150357760
    Abstract: Systems, methods and apparatuses involving a chip-to-chip communication channel, for reducing Far End Crosstalk (FEXT) through the novel concept of controlling FEXT magnitude and polarity of a component inside a channel, vias or within a connector by implementing broadside and edge couplings to offset cumulative FEXT in a channel, via-connector-via subsystem or a connector. The example implementations described herein can be applied to a chip-to-chip communication channel, mezzanine connectors, backplane connectors and any other connectors requiring via routing, and connector itself that can benefit from FEXT reduction.
    Type: Application
    Filed: May 8, 2015
    Publication date: December 10, 2015
    Inventors: Kunia AIHARA, Ching-Chao Huang
  • Publication number: 20140295702
    Abstract: An intermediate connection electrical connector includes a plurality of blades and a supporting member for supporting the blades arranged in an arrangement direction. The supporting member includes a surrounding wall portion for surrounding the blades and a regulating portion for positioning the blades. The surrounding wall portion includes a side wall portion and an edge wall portion. The side wall portion is at least partially formed of an electromagnetic wave absorbing material. The regulating portion is disposed inside the surrounding wall portion to define a blade accommodating space for accommodating the blades.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 2, 2014
    Applicant: Hirose Electric Co., Ltd.
    Inventors: Nobuhiro TAMAI, Toshiyuki TAKADA, Kunia AIHARA, Jeremy HUANG, Masakazu NAGATA