Abstract: The present invention relates to a multilayer wiring structure for a semiconductor device which can be designed without sacrificing either a micronization or electric properties, and a manufacturing method of the same. A first wiring layer and a third wiring layer are connected by a lower layer contact plug which fills a lower layer contact hole interposing a silicon nitride film spacer, and an upper layer contact plug which fills an upper layer contact hole interposing a silicon oxide film spacer. A second wiring layer divided into more than two portions by the upper layer contact hole near an upper end of the lower layer contact hole is connected by a ring-shaped conductive film spacer.

Abstract: A stabilized live vaccine containing a varicella virus and a stabilizer, wherein the vaccine is substantially free of Ca.sup.2+ ions and Mg.sup.2+ ions is described. This stabilized live vaccine is excellent in storage stability and heat resistance. Also described is an improved stabilizer for a live varicella vaccine, comprising at least gelatin or hydrolyzed gelatin, each being substantially free of Ca.sup.2+ ions and Mg.sup.2+ ions. The stabilizer can advantageously be used to stabilize a live vaccine containing a varicella virus. The substantial freedom of Ca.sup.2+ ions and Mg.sup.2+ ions can be attained by masking Ca.sup.2+ ions and Mg.sup.2+ ions present in a live vaccine containing a varicella virus and a stabilizer, with a chelating reagent, or by using as a stabilizer gelatin and/or a gelatin derivative after being purified to remove Ca.sup.2+ ions and/or Mg.sup.2+ ions contained therein.

Abstract: A storage node electrode is connected to a contact plug via an upper node contact hole. A lower cell plate electrode composed of an N type silicon film and an N type silicon film spacer is covered by the storage node electrode via a titanium oxide film as a lower capacitive insulating film and an upper cell plate electrode composed of an N type silicon film connected to the lower cell plate electrode covers the storage node electrode via a titanium oxide film as an upper capacitive insulating film. Thus, in a DRAM having a stacked and COB type memory, a surface ratio of the storage node electrode, contributing to a capacitor, is increased.

Abstract: Disclosed is a stabilized live vaccine containing a varicella virus and a stabilizer, wherein the vaccine is substantially free of Ca.sup.2+ ions and Mg.sup.2+ ions. This stabilized live vaccine is extremely excellent in storage stability and heat resistance. Also disclosed is an improved stabilizer for a live varicella vaccine, comprising at least one member selected from gelatin and hydrolyzed gelatin, each being substantially free of Ca.sup.2+ ions and Mg.sup.2+ ions. The stabilizer can advantageously be used to stabilize a live vaccine containing a varicella virus. The substantial freedom of Ca.sup.2+ ions and Mg.sup.2+ ions can be attained by masking Ca.sup.2+ ions and Mg.sup.2+ ions present in a live vaccine containing a varicella virus and a stabilizer, with a chelating reagent, or by using as a stabilizer gelatin and/or a gelatin derivative after being purified to remove Ca.sup.2+ ions and/or Mg.sup.2+ ions contained therein.

Abstract: A storage node electrode is connected to a contact plug via an upper node contact hole. A lower cell plate electrode composed of an N type silicon film and an N type silicon film spacer is covered by the storage node electrode via a titanium oxide film as a lower capacitive insulating film and an upper cell plate electrode composed of an N type silicon film connected to the lower cell plate electrode covers the storage node electrode via a titanium oxide film as an upper capacitive insulating film. Thus, in a DRAM having a stacked and COB type memory, a surface ratio of the storage node electrode, contributing to a capacitor, is increased.

Abstract: The present invention relates to a multilayer wiring structure for a semiconductor device which can be designed without sacrificing either a micronization or electric properties, and a manufacturing method of the same.A first wiring layer and a third wiring layer are connected by a lower layer contact plug which fills a lower layer contact hole interposing a silicon nitride film spacer, and an upper layer contact plug which fills an upper layer contact hole interposing a silicon oxide film spacer. A second wiring layer divided into more than two portions by the upper layer contact hole near an upper end of the lower layer contact hole is connected by a ring-shaped conductive film spacer.

Abstract: The invention provides a semiconductor substrate structure for semiconductor integrated circuit devices including a memory cell array area involving both stacked capacitors and transistors and a peripheral circuit area involving transistors. A portion of the device in the memory cell area has a larger thickness than that of the peripheral circuit area. The transistors involved in the memory cell array area possess different properties from that of the transistors involved in the peripheral circuit area. The substrate structure has a surface region comprising a first impurity concentration region underlying a recessed portion in the memory cell array area and an opposite region having a second impurity concentration from that of the high impurity concentration region so that a surface in the memory cell area exists at a lower level than that of a surface in the peripheral area.

Abstract: In a semiconductor device having a multilayer wiring, first and second lower wiring sections are formed on a base insulating film. An interlayer insulating layer covers the first and the second lower wiring sections. In the interlayer insulating layer, first and second contact holes are bored so as to reach the first and the second lower wiring sections, respectively. In the first and the second contact holes, first and second conductors are embedded so as to connect with the first and the second lower wiring sections, respectively. Formed on an upper surface of the interlayer insulating layer, a first upper wiring section interconnects with the first lower wiring section via the first conductor. The first upper wiring section has an upper surface and a side surface on which an upper insulating film and a side-wall insulating film are formed.

Abstract: A semiconductor device comprises a first conductive layer, an insulating layer formed on the first conductive layer, a plurality of contact holes formed through the insulating layer, a second conductive layer consisting of a plurality of pillar-shaped contacts each respectively formed in a corresponding one of the contact holes, the pillar-shaped contacts each respectively having a projecting portion projecting above the insulating layer, and a third conductive layer consisting of a plurality of conductive portions each respectively formed on the projecting portion of a corresponding one of the pillar-shaped contacts in a selectively growing manner.

Abstract: In a wiring and contact structure of a semiconductor device, a contact hole is formed to pass trough an interlayer insulating film and a gate oxide film and the contact hole is filled with a conductive material layer which projects from the interlayer insulating film. A first wiring layer is formed on the conductive material layer so as to partially overlap the contact hole, and an first insulating film is formed between the conductive material layer and the first wiring layer. A second insulating film having the same pattern as that of the first wiring layer is formed on the first wiring layer, and a third insulating film is formed as a side wall covering a side surface of the first wiring layer.

Abstract: In a semiconductor device having a multilayer wiring, first and second lower wiring sections are formed on a base insulating film. An interlayer insulating layer covers the first and the second lower wiring sections. In the interlayer insulating layer, first and second contact holes are bored so as to reach the first and the second lower wiring sections, respectively. In the first and the second contact holes, first and second conductors are embedded so as to connect with the first and the second lower wiring sections, respectively. Formed on an upper surface of the interlayer insulating layer, a first upper wiring section interconnects with the first lower wiring section via the first conductor. The first upper wiring section has an upper surface and a side surface on which an upper insulating film and a side-wall insulating film are formed.

Abstract: In a wiring and contact structure of a semiconductor device, a contact hole is formed to pass through an interlayer insulating film and a gate oxide film, and the contact hole is filled with a conductive material layer which projects from the interlayer insulating film. A first wiring layer is formed on the conductive material layer so as to partially overlap the contact hole, and an first insulating film is formed between the conductive material layer and the first wiring layer. A second insulating film having the same pattern as that of the first wiring layer is formed on the first wiring layer, and a third insulating film is formed as a side wall covering a side surface of the first wiring layer.

Abstract: A semiconductor device comprises a silicon via-plug within a fine via-hole in direct contact with an inner wall of the via-hole. A metal silicide layer is formed between an interconnection layer and the silicon plug as well as between the silicon plug and a diffused layer formed in a substrate. Shape defects and excessive stresses formed within a fine via-hole are reduced because the via-hole is filled with the silicon plug substantially without a metallic film or a metal silicide film on a sidewall. The metal silicide film is formed by a heat treatment through silicidation reaction.

Abstract: A semiconductor device having a capacitor includes a substrate, an insulating film formed on a surface of the substrate, a lower electrode formed on said insulating film, the lower electrode including a metal film the oxide of which is conductive, a dielectric film formed on said lower electrode, a sidewall spacer formed on sidewalls of said lower electrode and said dielectric film, the sidewall spacer being made of a dielectric material having a dielectric constant lower than the dielectric constant of said dielectric film, and an upper electrode formed on said dielectric film and the sidewall spacer.

Abstract: A semiconductor device adapted for reduction in size and increasing density is disclosed. The semiconductor device comprises an insulating layer having therein a contact hole in which a first conductive layer or a contact electrode is deposited for connecting a semiconductor active region with an overlying second conductive layer. The contact electrode has a top portion protruding from the insulating layer and a side surface in contact with the second conductive layer for increasing a contact area between the contact electrode and the second conductive layer. The top surface of the contact electrode may be provided with an insulating layer between the top surface and the interconnection wiring layer formed from the second conductive layer in order to avoid etching of the contact electrode and underlying semiconductor active region during etching of the second conductive layer, even in the case of misalignment of the contact electrode with the interconnection wiring layer.

Abstract: The invention provides a semiconductor substrate structure for semiconductor integrated circuit devices including a memory cell array area involving both stacked capacitors and transistors and a peripheral circuit area involving transistors. A portion of the device in the memory cell area has a larger thickness than that of the peripheral circuit area. The transistors involved in the memory cell array area possess different properties from that of the transistors involved in the peripheral circuit area. The substrate structure has a surface region comprising a first impurity concentration region underlying a recessed portion in the memory cell array area and an opposite region having a second impurity concentration from that of the high impurity concentration region so that a surface in the memory cell area exists at a lower level than that of a surface in the peripheral area.

Abstract: A p.sup.+ -diffusion layer is formed on a surface of a p-type silicon substrate in self-alignment with a groove 7 defined in the p-type silicon substrate, and a thin insulating film is formed on the groove and the p.sup.+ -diffusion layer in self-alignment therewith, the thick insulating film having side walls. A self-aligned n.sup.+ -diffusion layer has terminal edges spaced from terminal edges of the p.sup.+ -diffusion layer for minimizing any leakage current flowing between these terminal edges.

Abstract: The invention provides a semiconductor substrate structure for semiconductor integrated circuit devices including a memory cell array area involving both stacked capacitors and transistors and a peripheral circuit area involving transistors. A portion of the device in the memory cell area has a larger thickness than that of the peripheral circuit area. The transistors involved in the memory cell array area possess different properties from that of the transistors involved in the peripheral circuit area. The substrate structure has a surface region comprising a first impurity concentration region underlying a recessed portion in the memory cell array area and an opposite region having a second impurity concentration from that of the high impurity concentration region so that a surface in the memory cell area exists at a lower level than that of a surface in the peripheral area.

Abstract: A dynamic random access memory cell with a stacked capacitor comprises a switching transistor shifted between on and off states, an inter-level insulating film covering the switching transistor and having a contact window and a storage capacitor provided on the inter-level insulating film and coupled to the switching transistor through the contact window, and the storage capacitor includes a lower electrode having a generally convex top surface and a pug portion penetrating through the contact window so as to electrically connect with the switching transistor, a thin dielectric film covering the generally convex top surface of the lower electrode and an upper electrode formed on the thin dielectric film, since the thin dielectric film extends along the generally convex top surface, a conformal coverage takes place for producing uniform electric field across the thin dielectric film, thereby decreasing undesirable leakage current flowing between the lower and upper electrodes.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising an insulated gate MOS transistor and a stacked capacitor. The stacked capacitor having a lower electrode and an oppositely disposed upper electrode whereby the lower electrode has an insulating film in its interior, thereby making it possible to increase the capacitance of the stacked capacitor without increasing the surface area of the electrode.