Abstract: A polyarylene sulfide resin composition characterized by comprising a polyarylene sulfide resin, and an olefinic copolymer comprising an ?-olefin-derived structural unit and an ?,?-unsaturated acid glycidyl ester-derived structural unit, wherein the olefinic copolymer content is at least 1.0 parts by mass and less than 5.0 parts by mass with respect to 100 parts by mass of the polyarylene sulfide resin, a melt viscosity of the polyarylene sulfide resin measured at 310° C. and a shear rate of 1216 sec?1 is at least 70 Pa·s and at most 300 Pa·s, and a flow length for a width of 20 mm and a thickness of 1 mm, at a cylinder temperature of 320° C., an injection pressure of 100 MPa and a mold temperature of 150° C., is at least 80 mm and at most 200 mm.

Abstract: A polyarylene sulfide resin composition characterized by comprising a polyarylene sulfide resin, and an olefinic copolymer comprising an ?-olefin-derived structural unit and an ?,?-unsaturated acid glycidyl ester-derived structural unit, wherein the olefinic copolymer content is at least 1.0 parts by mass and less than 5.0 parts by mass with respect to 100 parts by mass of the polyarylene sulfide resin, a melt viscosity of the polyarylene sulfide resin measured at 310° C. and a shear rate of 1216 sec?1 is at least 70 Pa·s and at most 300 Pa·s, and a flow length for a width of 20 mm and a thickness of 1 mm, at a cylinder temperature of 320° C., an injection pressure of 100 MPa and a mold temperature of 150° C., is at least 80 mm and at most 200 mm.

Abstract: A laminated holographic recording medium having (a) a first substrate having a through-hole and (b) a solid polymer matrix layer that records holographic data laminated to the first substrate and a method of manufacturing thereof are disclosed. The method of manufacturing preferably requires injecting a precursor material through the through-hole and polymerizing the precursor material in contact with the first substrate to form the polymer matrix layer.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, an SATA I/F connected to an SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register (TFR). The sequence controller suspends transmission of a register FIS corresponding to an ATA packet command issued by a host to a device, and performs a dummy setting that causes the host to issue an ATAPI packet command using the TFR. The sequence controller transmits the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command.

Abstract: A data transfer control device having: a hub dedicated data storage section which stores a packet transferred between the data transfer control device and a hub; a packet transmission section which cyclically issues a token packet to the hub for asking whether the state of the hub has changed or not; a packet reception section which receives a response packet sent from the hub in response to the token packet; and a transfer controller which writes the response packet received by the packet reception section into the hub dedicated data storage section, and generates an interrupt which indicates that the state of the hub has changed.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, an SATA I/F connected to an SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register (TFR). The sequence controller suspends transmission of a register FIS corresponding to an ATA packet command issued by a host to a device, and performs a dummy setting that causes the host to issue an ATAPI packet command using the TFR. The sequence controller transmits the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command.

Abstract: When transfer condition information is set and the start of automatic control transfer is instructed, a transfer controller (host controller) automatically issues a setup stage transaction and automatically transfers a setup stage packet, then, if there is data to be transferred, it automatically issues a data stage transaction and automatically transfers a data stage packet. It then automatically issues a status stage transaction and automatically transfers a status stage packet. Device request data, the total size of transfer data, data stage present/absent information, transfer direction in the data stage, and maximum packet size are set in transfer condition registers. A pipe region is allocated in the packet buffer during host operation of USB On-The-Go.

Abstract: Aspects of the invention can provide a data transfer control device and electronic equipment that can achieve to switch supplying power through a VBUS. The transfer controller can transmit a switching request packet of supplying power through a VBUS to a type-B plug connected side (a type-B device side). In the case when the transfer controller can receive a switching acknowledgment packet of supplying power through the VBUS, the transfer controller can instruct a power supply switching circuit to stop a power supply through the VBUS. A monitoring the voltage level of the VBUS can be stopped before stopping the power supply through the VBUS. A transfer controller can receive the switching request packet of supplying power through the VBUS from the type-A plug connected side (a type-A device side).

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, a SATA I/F connected to a SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register that is a pseudo register provided to implement a PATA/SATA bus bridge, and the SATA I/F includes a shadow task file register, a register value being transferred between the shadow task file register and the task file register.

Abstract: When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF packets is disabled and non-periodic data is transferred. If there is no non-periodic data to be transferred, a SOF packet is transferred in the frame period, even if the second mode has been set. During host operation with USB on-the-go (OTG), pipe regions are allocated to the packet buffer, and non-periodic data is transferred automatically to or from end points while the periodic transfer of SOF packets is disabled. When all of the automatic transfer instruction signals of the pipe regions are inactive, SOF packets are transferred periodically even if the second mode has been set.

Abstract: A laminated holographic recording medium having (a) a first substrate having a through-hole and (b) a solid polymer matrix layer that records holographic data laminated to the first substrate and a method of manufacturing thereof are disclosed. The method of manufacturing preferably requires injecting a precursor material through the through-hole and polymerizing the precursor material in contact with the first substrate to form the polymer matrix layer.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: A signal state detection circuit of a data transfer control device notifies a processing of results detected by a line state detection circuit or a power supply line detection circuit by using an interrupt signal. The processing sets a state command corresponding to a state of a transition destination judged based on the notified detection results in a control register of a state controller. A state command decoder decodes the state command set in the control register and generates a control signal. A signal line control circuit controls a signal state of at least one of signal lines formed of data signal lines (D+ and D?) and power supply lines (VBUS and GND) based on the control signal.

Abstract: Aspects of the invention can provide a data transfer control device that can switchover VBUS feed voltage. The transfer controller can send a switchover request packet to switch over a VBUS feed voltage to a plug B coupling side (device B side). When the transfer controller receives a switchover consent packet, it can instruct a feed switch circuit to switch over from normal voltage feed to low voltage feed. Then, monitor of the VBUS normal voltage level can be stopped and monitor of the VBUS low voltage level is started. The transfer controller receives the switchover request packet to switch over the VBUS feed voltage from the plug A coupling side (device A side). If it agrees to the switchover, it can send the switchover consent packet. And then, the monitor of the VBUS normal voltage level can be stopped and the monitor of the VBUS low voltage level is started. The switchover request packet and the switchover consent packet can be sent by a control transfer.

Abstract: Aspects of the invention can provide a data transfer control device and electronic equipment that can achieve to switch supplying power through a VBUS. The transfer controller can transmit a switching request packet of supplying power through a VBUS to a type-B plug connected side (a type-B device side). In the case when the transfer controller can receive a switching acknowledgment packet of supplying power through the VBUS, the transfer controller can instruct a power supply switching circuit to stop a power supply through the VBUS. A monitoring the voltage level of the VBUS can be stopped before stopping the power supply through the VBUS. A transfer controller can receive the switching request packet of supplying power through the VBUS from the type-A plug connected side (a type-A device side).

Abstract: A data transfer control device having: a hub dedicated data storage section which stores a packet transferred between the data transfer control device and a hub; a packet transmission section which cyclically issues a token packet to the hub for asking whether the state of the hub has changed or not; a packet reception section which receives a response packet sent from the hub in response to the token packet; and a transfer controller which writes the response packet received by the packet reception section into the hub dedicated data storage section, and generates an interrupt which indicates that the state of the hub has changed.

Abstract: When an electronic instrument Q is in normal operating mode and set to be slave, power from a rechargeable battery or an external power source is supplied to a data transfer control circuit, and when the electronic instrument Q is in charge mode and set to be slave, power from VBUS is supplied thereto to charge a rechargeable battery. When an external power source can be used in charge mode, power from the external power source is supplied to the rechargeable battery instead of from VBUS. When an electronic instrument P is in normal operating mode and set to be master, power from a rechargeable battery or an external power source is supplied to the data transfer control circuit and the electronic instrument Q; and when the electronic instrument P is in charge mode and set to be master, power from the rechargeable battery or the external power source is supplied to the electronic instrument Q through the VBUS in order to charge a rechargeable battery of the electronic instrument Q.

Abstract: When transfer condition information is set and the start of automatic control transfer is instructed, a transfer controller (host controller) automatically issues a setup stage transaction and automatically transfers a setup stage packet, then, if there is data to be transferred, it automatically issues a data stage transaction and automatically transfers a data stage packet. It then automatically issues a status stage transaction and automatically transfers a status stage packet. Device request data, the total size of transfer data, data stage present/absent information, transfer direction in the data stage, and maximum packet size are set in transfer condition registers. A pipe region is allocated in the packet buffer during host operation of USB On-The-Go.

Abstract: When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF packets is disabled and non-periodic data is transferred. If there is no non-periodic data to be transferred, a SOF packet is transferred in the frame period, even if the second mode has been set. During host operation with USB on-the-go (OTG), pipe regions are allocated to the packet buffer, and non-periodic data is transferred automatically to or from end points while the periodic transfer of SOF packets is disabled. When all of the automatic transfer instruction signals of the pipe regions are inactive, SOF packets are transferred periodically even if the second mode has been set.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.