Patents by Inventor Kuniharu Muto
Kuniharu Muto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369179Abstract: A semiconductor device includes: a die pad having an upper surface facing a semiconductor chip, a metal film formed on the upper surface, and a bonding material formed so as to cover the metal film. Here, the upper surface has: a first region overlapping the semiconductor chip, a second region not overlapping the semiconductor chip, a third region included in the first region and covered with the metal film, and a fourth region included in the first region and adjacent to the third region and also not covered with the metal film. Also, the semiconductor chip is mounted on the die pad such that a center of the semiconductor chip overlaps the third region. Further, an area of the third region is greater than or equal to 11% of an area of the first region, and less than or equal to 55% of the area of the first region.Type: ApplicationFiled: February 22, 2023Publication date: November 16, 2023Inventors: Katsuhiko KITAGAWA, Takehiko MAEDA, Kuniharu MUTO, Takeshi MIYAKOSHI
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Patent number: 11037847Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.Type: GrantFiled: January 7, 2020Date of Patent: June 15, 2021Assignee: Renesas Electronics CorporationInventors: Kuniharu Muto, Koji Bando
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Patent number: 10811345Abstract: Assembly of the semiconductor device includes the following steps: (a) mounting a semiconductor chip on the bottom electrode 40; (b) mounting the top electrode 30 on the semiconductor chip; (c) forming a sealing body 70 made of resin and provided with a convex portion 74 so as to cover the semiconductor chip; and (d) exposing the electrode surface 31 of the top electrode 30 on the top surface of the sealing body 70 and exposing the electrode surface 41 of the bottom electrode 40 on the back surface of the sealing body 70. In the step (d), at least one of the electrode surface 31 and the electrode surface 41 is exposed from the sealing body 70 by irradiating at least one of the front surface and the back surface of the sealing body 70 with the laser 110.Type: GrantFiled: May 13, 2019Date of Patent: October 20, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kuniharu Muto, Hideyuki Nishikawa
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Publication number: 20200144147Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.Type: ApplicationFiled: January 7, 2020Publication date: May 7, 2020Inventors: Kuniharu MUTO, Koji BANDO
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Patent number: 10573604Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.Type: GrantFiled: October 4, 2018Date of Patent: February 25, 2020Assignee: Renesas Electronics CorporationInventors: Kuniharu Muto, Ryo Kanda
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Patent number: 10566258Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.Type: GrantFiled: May 3, 2018Date of Patent: February 18, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kuniharu Muto, Koji Bando
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Publication number: 20190378785Abstract: Assembly of the semiconductor device includes the following steps: (a) mounting a semiconductor chip on the bottom electrode 40; (b) mounting the top electrode 30 on the semiconductor chip; (c) forming a sealing body 70 made of resin and provided with a convex portion 74 so as to cover the semiconductor chip; and (d) exposing the electrode surface 31 of the top electrode 30 on the top surface of the sealing body 70 and exposing the electrode surface 41 of the bottom electrode 40 on the back surface of the sealing body 70. In the step (d), at least one of the electrode surface 31 and the electrode surface 41 is exposed from the sealing body 70 by irradiating at least one of the front surface and the back surface of the sealing body 70 with the laser 110.Type: ApplicationFiled: May 13, 2019Publication date: December 12, 2019Inventors: Kuniharu MUTO, Hideyuki NISHIKAWA
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Patent number: 10284109Abstract: An electronic device includes a first substrate, a wiring substrate (second substrate) disposed over the first substrate, and an enclosure (case) in which the first substrate and the wiring substrate are accommodated and that has a first side and a second side. A driver component (semiconductor component) is mounted on the wiring substrate. A gate electrode of a first semiconductor component is electrically connected to the driver component via a lead disposed on a side of the first side and a wiring disposed between the driver component and the first side. A gate electrode of a second semiconductor component is electrically connected to the driver component via a lead disposed on a side of the second side and a wiring disposed between the driver component and the second side.Type: GrantFiled: February 8, 2018Date of Patent: May 7, 2019Assignee: Renesas Electronics CorporationInventors: Koji Bando, Kuniharu Muto, Hideaki Sato
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Publication number: 20190035745Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.Type: ApplicationFiled: October 4, 2018Publication date: January 31, 2019Inventors: Kuniharu MUTO, Ryo KANDA
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Publication number: 20190006258Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.Type: ApplicationFiled: May 3, 2018Publication date: January 3, 2019Inventors: Kuniharu MUTO, Koji BANDO
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Patent number: 10128200Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.Type: GrantFiled: December 6, 2017Date of Patent: November 13, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kuniharu Muto, Ryo Kanda
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Publication number: 20180241319Abstract: An electronic device includes a first substrate, a wiring substrate (second substrate) disposed over the first substrate, and an enclosure (case) in which the first substrate and the wiring substrate are accommodated and that has a first side and a second side. A driver component (semiconductor component) is mounted on the wiring substrate. A gate electrode of a first semiconductor component is electrically connected to the driver component via a lead disposed on a side of the first side and a wiring disposed between the driver component and the first side. A gate electrode of a second semiconductor component is electrically connected to the driver component via a lead disposed on a side of the second side and a wiring disposed between the driver component and the second side.Type: ApplicationFiled: February 8, 2018Publication date: August 23, 2018Inventors: Koji BANDO, Kuniharu MUTO, Hideaki SATO
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Publication number: 20180182719Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.Type: ApplicationFiled: December 6, 2017Publication date: June 28, 2018Inventors: Kuniharu MUTO, Ryo KANDA
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Publication number: 20180138828Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Kuniharu MUTO, Koji BANDO, Takamitsu KANAZAWA, Ryo KANDA, Akihiro TAMURA, Hirobumi MINEGISHI
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Patent number: 9906165Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.Type: GrantFiled: June 28, 2016Date of Patent: February 27, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kuniharu Muto, Koji Bando, Takamitsu Kanazawa, Ryo Kanda, Akihiro Tamura, Hirobumi Minegishi
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Publication number: 20170033710Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.Type: ApplicationFiled: June 28, 2016Publication date: February 2, 2017Inventors: Kuniharu MUTO, Koji BANDO, Takamitsu KANAZAWA, Ryo KANDA, Akihiro TAMURA, Hirobumi MINEGISHI
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Publication number: 20120034742Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.Type: ApplicationFiled: October 19, 2011Publication date: February 9, 2012Inventors: Kuniharu Muto, Toshiyuki Hata, Hiroshi Sato, Hiroi Oka, Osamu Ikeda
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Publication number: 20100181628Abstract: Prevention of disconnection of a bonding wire resulting from adhesive interface delamination between a resin and a leadframe, and improvement of joint strength of the resin and the leadframe are achieved in a device manufactured by a low-cost and simple processing. A boss is provided on a source lead by a stamping processing, and a support pillar is provided in a concave portion on a rear side of the source lead in order to prevent ultrasonic damping upon joining the bonding wire onto the boss, so that an insufficiency of the joint strength between the bonding wire and the source lead is prevented. Also, a continuous bump is provided on the boss so as to surround a joint portion between the source lead and the bonding wire, so that disconnection of the bonding wire resulting from delamination between the resin and the source lead is prevented.Type: ApplicationFiled: January 21, 2010Publication date: July 22, 2010Applicant: Renesas Technology Corp.Inventors: Kenya Kawano, Kisho Ashida, Kuniharu Muto, Ichio Shimizu, Tomibumi Inoue
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Publication number: 20100105174Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.Type: ApplicationFiled: January 5, 2010Publication date: April 29, 2010Inventors: Kuniharu Muto, Toshiyuki Hata, Hiroshi Sato, Hiroi Oka, Osamu Ikeda
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Patent number: 7667307Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.Type: GrantFiled: March 27, 2008Date of Patent: February 23, 2010Assignee: Renesas Technology Corp.Inventors: Kuniharu Muto, Toshiyuki Hata, Hiroshi Sato, Hiroi Oka, Osamu Ikeda