Patents by Inventor Kuniharu Takei

Kuniharu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11846603
    Abstract: The present invention provides a chemical sensor that can be manufactured at low cost and has high detection sensitivity.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 19, 2023
    Assignee: UNIVERSITY PUBLIC CORPORATION OSAKA
    Inventors: Kuniharu Takei, Shogo Nakata
  • Publication number: 20210190722
    Abstract: The present invention provides a chemical sensor that can be manufactured at low cost and has high detection sensitivity.
    Type: Application
    Filed: May 22, 2019
    Publication date: June 24, 2021
    Inventors: Kuniharu TAKEI, Shogo NAKATA
  • Patent number: 9593014
    Abstract: A method of conductively coupling a carbon nanostructure and a metal electrode is provided that includes disposing a carbon nanostructure on a substrate, depositing a carbon-containing layer on the carbon nanostructure, according to one embodiment, and depositing a metal electrode on the carbon-containing layer. Further provided is a conductively coupled carbon nanostructure device that includes a carbon nanostructure disposed on a substrate, a carbon-containing layer disposed on the carbon nanostructure and a metal electrode disposed on the carbon-containing layer, where a low resistance coupling between the carbon nanostructure and metal elements is provided.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: March 14, 2017
    Assignees: The Board of Trustees of the Leland Stanford Junior University, The Regents of the University of California
    Inventors: Yang Chai, Arash Hazeghi, Kuniharu Takei, Ali Javey, H. S. Philip Wong
  • Patent number: 9299940
    Abstract: This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: March 29, 2016
    Assignee: The Regents of the University of California
    Inventors: Kuniharu Takei, Toshitake Takahashi, Ali Javey
  • Patent number: 9076719
    Abstract: Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a dopant-containing polymer and a non-polar solvent on a substrate; and annealing the substrate at a temperature of 750 to 1300° C. for 1 second to 24 hours to diffuse the dopant into the substrate; wherein the dopant-containing polymer is a polymer having a covalently bound dopant atom; wherein the dopant-containing polymer is free of nitrogen and silicon; and wherein the method is free of a step of forming an oxide capping layer over the coating prior to the annealing step.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: July 7, 2015
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, ROHM AND HAAS ELECTRONICS MATERIALS LLC
    Inventors: Rachel A. Segalman, Megan L. Hoarfrost, Ali Javey, Kuniharu Takei, Peter Trefonas, III
  • Publication number: 20150056793
    Abstract: Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a dopant-containing polymer and a non-polar solvent on a substrate; and annealing the substrate at a temperature of 750 to 1300° C. for 1 second to 24 hours to diffuse the dopant into the substrate; wherein the dopant-containing polymer is a polymer having a covalently bound dopant atom; wherein the dopant-containing polymer is free of nitrogen and silicon; and wherein the method is free of a step of forming an oxide capping layer over the coating prior to the annealing step.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicants: Rohm and Haas Electronic Materials LLC, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Rachel A. Segalman, Megan L. Hoarfrost, Ali Javey, Kuniharu Takei, Peter Trefonas, III
  • Publication number: 20140124737
    Abstract: This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.
    Type: Application
    Filed: October 28, 2013
    Publication date: May 8, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kuniharu Takei, Toshitake Takahashi, Ali Javey
  • Patent number: 8525228
    Abstract: Semiconductor-on-insulator (XOI) structures and methods of fabricating XOI structures are provided. Single-crystalline semiconductor is grown on a source substrate, patterned, and transferred onto a target substrate, such as a Si/SiO2 substrate, thereby assembling an XOI substrate. The transfer process can be conducted through a stamping method or a bonding method. Multiple transfers can be carried out to form heterogenous compound semiconductor devices. The single-crystalline semiconductor can be II-IV or III-V compound semiconductor, such as InAs. A thermal oxide layer can be grown on the patterned single crystalline semiconductor, providing improved electrical characteristics and interface properties. In addition, strain tuning is accomplished via a capping layer formed on the single-crystalline semiconductor before transferring the single-crystalline semiconductor to the target substrate.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: September 3, 2013
    Assignee: The Regents of the University of California
    Inventors: Ali Javey, Hyunhyub Ko, Kuniharu Takei
  • Publication number: 20130059134
    Abstract: A method of conductively coupling a carbon nanostructure and a metal electrode is provided that includes disposing a carbon nanostructure on a substrate, depositing a carbon-containing layer on the carbon nanostructure, according to one embodiment, and depositing a metal electrode on the carbon-containing layer. Further provided is a conductively coupled carbon nanostructure device that includes a carbon nanostructure disposed on a substrate, a carbon-containing layer disposed on the carbon nanostructure and a metal electrode disposed on the carbon-containing layer, where a low resistance coupling between the carbon nanaostructure and metal elements is provided.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Inventors: Yang Chai, Arash Hazeghi, Kuniharu Takei, Ali Javey, H.S. Philip Wong
  • Publication number: 20120061728
    Abstract: Semiconductor-on-insulator (XOI) structures and methods of fabricating XOI structures are provided. Single-crystalline semiconductor is grown on a source substrate, patterned, and transferred onto a target substrate, such as a Si/SiO2 substrate, thereby assembling an XOI substrate. The transfer process can be conducted through a stamping method or a bonding method. Multiple transfers can be carried out to form heterogenous compound semiconductor devices. The single-crystalline semiconductor can be II-IV or III-V compound semiconductor, such as InAs. A thermal oxide layer can be grown on the patterned single crystalline semiconductor, providing improved electrical characteristics and interface properties. In addition, strain tuning is accomplished via a capping layer formed on the single-crystalline semiconductor before transferring the single-crystalline semiconductor to the target substrate.
    Type: Application
    Filed: July 1, 2011
    Publication date: March 15, 2012
    Applicant: The Regents of the University of California
    Inventors: ALI JAVEY, HYUNHYUB KO, KUNIHARU TAKEI
  • Publication number: 20120016261
    Abstract: A hollow microtube structure capable of being used as a minimally invasive electrode, a production method thereof, and a biopsy device using the hollow microtube structure. The hollow microtube structure includes a semiconductor substrate and at least one hollow tube formed on a surface of the semiconductor substrate. The hollow tube includes a metal coating film layer on the inner surface and an electrically insulating coating film layer on the outer surface. The semiconductor substrate includes a through hole communicated with an interior of a hollow tube at a location where the hollow tube is formed. The production method includes an etching, a sacrificial layer forming, a metal coating film layer forming, an electrically insulating coating film layer forming, a tip portion removing, and a piercing.
    Type: Application
    Filed: March 19, 2010
    Publication date: January 19, 2012
    Applicant: NAT. UNIV. CORP. TOYOHASHI UNIV. OF TECHNOLOGY
    Inventors: Makoto Ishida, Takeshi Kawano, Takahiro Kawashima, Kuniharu Takei