Abstract: A neural network circuit and a processing scheme using the neural network circuit in which a synapse calculation for each input value and a corresponding synapse weight of each input value which are expressed by binary bit sequences is carried out by using a sequentially specified bit of the corresponding synapse weight, a summation calculation for sequentially summing synapse calculation results for the input values is carried out to obtain a summation value, a prescribed nonlinear processing is applied to the obtained summation value so as to determine the output value, whether the obtained summation value reached to a saturation region of a transfer characteristic of the prescribed nonlinear processing is judged, the synapse calculation and the summation calculation are controlled to sequentially carry out the synapse calculation from upper bits of the corresponding synapse weight, and to stop the synapse calculation and the summation calculation whenever it is judged that the obtained summation value reac

Abstract: A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof being inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients being inputted into an addition circuit and accumulated, and this accumulation result determining the output valve. A threshold valve circuit determines the final output value, according to a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can include simply EX-OR logic (exclusive OR) gates.

Abstract: A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof being inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients being inputted into an addition circuit and accumulated, and this accumulation result determining the output value. A threshold value circuit determines the final output value, according to a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can include simply EX-OR logic (exclusive OR) gates.

Abstract: A neural network circuit, in which a number n of weight coefficients (Wl-wn) corresponding to a number n of inputs are provided, subtraction circuits determine the difference between inputs and the weight coefficients in each input terminal, the result thereof is inputted into absolute value circuits, all calculation results of the absolute value circuts corresponding to the inputs and the weight coefficients are inputted into an addition circuit and accumulated, and this accumulation result determines the output value. The threshold value circuit, which determines the final output value, has characteristics of a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can comprise simply EX-OR logic (exclusive OR) gates.

Abstract: An oversampling converter includes first and second integrators for integrating a difference between an input terminal voltage and feedback voltages, first and second quantizers for quantizing outputs from the first and second integrators, respectively, first and second feedback paths for feeding back as the feedback voltages outputs from the first quantizer to the input sides of the first and second integrators, a differentiator arranged at an output side of the second quantizer, an adder for adding an output from the differentiator and the output from the first quantizer, and a circuit for supplying an output from the first integrator to an input terminal of the second integrator. Two or more quantization loops may be used. When the oversampling converter is used as an A/D converter, A/D converters are arranged in the first and second feedback paths.

Abstract: In a switched capacitor circuit, in order to eliminate leakage of a power supply noise component to a signal line through an input capacitance of an operation amplifier, (1) an operating current of at least a first, differential stage among stages of the operational amplifier is regulated by a current regulation bias circuit, and (2) a power supply noise component having the same phase as that of an input signal is applied to the gate of a transistor of a gain stage, thereby stabilizing the operating point. In order to eliminate leakage of the power supply noise component to the signal line through a parasitic capacitance of an analog switch, (3) a dummy switch is used to detect a signal corresponding to the leakage component of the power supply noise component to the signal line, and an inverted signal having the opposite phase to that of the signal corresponding to the leakage component is applied to a substrate of the analog switch, thereby cancelling the actual leakage component.