Patents by Inventor Kunihiko Fukuchi

Kunihiko Fukuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7883912
    Abstract: According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a portion of the gate insulating film where is not located under the semiconductor layer is removed during manufacturing steps of the present invention.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: February 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunihiko Fukuchi, Gen Fujii, Osamu Nakamura, Shinji Maekawa
  • Patent number: 7709844
    Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 ?m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: May 4, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Publication number: 20090325333
    Abstract: According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a portion of the gate insulating film where is not located under the semiconductor layer is removed during manufacturing steps of the present invention.
    Type: Application
    Filed: September 2, 2009
    Publication date: December 31, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kunihiko Fukuchi, Gen Fujii, Osamu Nakamura, Shinji Maekawa
  • Patent number: 7601994
    Abstract: According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a portion of the gate insulating film where is not located under the semiconductor layer is removed during manufacturing steps of the present invention.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: October 13, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunihiko Fukuchi, Gen Fujii, Osamu Nakamura, Shinji Maekawa
  • Patent number: 7470580
    Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: December 30, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Kunihiko Fukuchi
  • Patent number: 7465966
    Abstract: A new film formation method that makes it possible to form a film with a little concentration of contaminants from a material and to form a film on a low heat-resistant member is proposed. Further, a method for forming a film that can keep semiconductor properties is proposed. In the film formation method of the present invention, a first film that is to be a target is formed by employing plasma CVD, and the first film is sputtered, thereby forming the second film on a surface of the substrate to be processed in one chamber. By employing the film formation method of the present invention for a protective film of a semiconductor element, deterioration of a semiconductor device can be controlled.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: December 16, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Taketomi Asami, Kunihiko Fukuchi, Satoshi Toriumi
  • Patent number: 7416977
    Abstract: An object of the present invention is to provide a method for manufacturing a display device with few steps and high yield. One feature of the invention is to form a first mask pattern having low wettability over a conductive layer, form a second mask pattern having high wettability over the conductive layer using the first mask pattern as a mask, and form a mask pattern for etching the conductive layer by removing the first mask pattern. Another feature is to form a pixel electrode by etching the conductive layer.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: August 26, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunihiko Fukuchi, Toshiyuki Isa, Gen Fujii
  • Patent number: 7371623
    Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: May 13, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Patent number: 7358183
    Abstract: The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present invention, a composition including a conductive material is discharged locally and an electric conductor to function as a pillar is formed on a first pattern over a substrate, an insulator is formed to cover the electric conductor, the insulator is etched to expose a top surface of the electric conductor, and a second pattern is formed on the top surface of electric conductor that is exposed.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: April 15, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kunihiko Fukuchi
  • Publication number: 20070173053
    Abstract: The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present invention, a composition including a conductive material is discharged locally and an electric conductor to function as a pillar is formed on a first pattern over a substrate, an insulator is formed to cover the electric conductor, the insulator is etched to expose a top surface of the electric conductor, and a second pattern is formed on the top surface of electric conductor that is exposed.
    Type: Application
    Filed: April 2, 2007
    Publication date: July 26, 2007
    Inventor: Kunihiko Fukuchi
  • Publication number: 20070111511
    Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.
    Type: Application
    Filed: January 11, 2007
    Publication date: May 17, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Kunihiko Fukuchi
  • Patent number: 7202155
    Abstract: The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present invention, a composition including a conductive material is discharged locally and an electric conductor to function as a pillar is formed on a first pattern over a substrate, an insulator is formed to cover the electric conductor, the insulator is etched to expose a top surface of the electric conductor, and a second pattern is formed on the top surface of electric conductor that is exposed.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kunihiko Fukuchi
  • Publication number: 20070057258
    Abstract: According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a portion of the gate insulating film where is not located under the semiconductor layer is removed during manufacturing steps of the present invention.
    Type: Application
    Filed: November 5, 2004
    Publication date: March 15, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunihiko Fukuchi, Gen Fujii, Osamu Nakamura, Shinji Maekawa
  • Patent number: 7163854
    Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: January 16, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Kunihiko Fukuchi
  • Publication number: 20060278878
    Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 ?m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
    Type: Application
    Filed: July 5, 2006
    Publication date: December 14, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Patent number: 7078768
    Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400–700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1–5 ?m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: July 18, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi
  • Publication number: 20060151314
    Abstract: It is an object to provide a sputtering system that enables forming a high-quality thin film including no impurity, and it is also an object of the present invention to provide a method for manufacturing a high-quality thin film with the sputtering system. The present invention provides a sputtering system including a target material and a part coated with a spray material including the same material as the target material. The present invention also provides a method for manufacturing a thin film including one of a target material, oxide of the target material, and nitride of the target material, which includes preparing a sputtering system including the target material and a part coated with a spray material including the same material as the target material, and applying high-frequency power in an atmosphere including rare gas.
    Type: Application
    Filed: March 13, 2006
    Publication date: July 13, 2006
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kunihiko Fukuchi, Akihiko Koura, Tetsunori Maruyama, Toru Takayama
  • Publication number: 20050244995
    Abstract: An object of the present invention is to provide a method for manufacturing a display device with few steps and high yield. One feature of the invention is to form a first mask pattern having low wettability over a conductive layer, form a second mask pattern having high wettability over the conductive layer using the first mask pattern as a mask, and form a mask pattern for etching the conductive layer by removing the first mask pattern. Another feature is to form a pixel electrode by etching the conductive layer.
    Type: Application
    Filed: April 20, 2005
    Publication date: November 3, 2005
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunihiko Fukuchi, Toshiyuki Isa, Gen Fujii
  • Publication number: 20050037614
    Abstract: The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present invention, a composition including a conductive material is discharged locally and an electric conductor to function as a pillar is formed on a first pattern over a substrate, an insulator is formed to cover the electric conductor, the insulator is etched to expose a top surface of the electric conductor, and a second pattern is formed on the top surface of electric conductor that is exposed.
    Type: Application
    Filed: August 5, 2004
    Publication date: February 17, 2005
    Inventor: Kunihiko Fukuchi
  • Patent number: 6822293
    Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 &mgr;m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: November 23, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi