Abstract: The modular operation apparatus of the present invention that enables to improve the tamper resistance to the side channel attacks includes an operator that carries out a Montgomery multiplication according to one of a first multiplicand and a second multiplicand, a multiplier, and a divisor, a first multiplicand register that stores an operation result of the Montgomery multiplication as the first multiplicand, a subtractor that subtracts the divisor from the operation result of the Montgomery multiplication, a second multiplicand register that stores a subtraction result of the subtractor as the second multiplicand, and a selector that outputs one of a value of the first multiplicand register and a value of the second multiplicand register according to a comparison result between the operation result of the Montgomery multiplication and the divisor.

Abstract: The bit strings of multipliers B and N are converted through the use of the Booth's algorithm in units composed of a predetermined number of bits and the operation of A×B+u×N is executed by a carry save adder using the value of an integral multiple of multiplicand A corresponding to the multiplication result of the values of the converted multiplier B and multiplicand A and also the value of an integral multiple of multiplicand u corresponding to the multiplication result of the values of the converted multiplier N and multiplicand u. The operation result of A×B+u×N supplied from the carry save adder are added to the operation result in the past of A×B+u×N through the use of an adder and the added result is supplied as the result of a modular-multiplication operation S=S+A×B+u×N.

Abstract: Either a multiplicand A or 0 is selected, depending on the value of multiplier B supplied in a unit composed of q bits through the use of selectors, and the selected result is provided, and either a multiplicand u or 0 is selected, depending on the value of multiplier N supplied in a unit composed of q bits through the use of selectors, and the selected result is provided. A carry save adder implements the operation of A×B+u×N making use of the values successively supplied from the selectors. To the operation result of A×B+u×N supplied from the carry save adder in a unit composed of q bits is added the operation result of A×B+u×N in the past supplied in a unit composed of q bits and the added result is issued as a result of the modular-multiplication operation S.

Abstract: A data processing device such as an IC card is switchable between a terminal mode in which drive electric power and signals are supplied via exposed connection terminals and an RF mode in which drive electric power and signals are supplied via built-in antennas. The data processing device has an internal circuit for being supplied with drive electric power and signals from either the connection terminals or the antennas depending on the mode to which the internal circuit has been set. The internal circuit typically comprises a microprocessor. The data processing device also has a mode detector for setting the internal circuit to the RF mode in response to a predetermined radio wave applied to the antennas and setting the internal circuit to the terminal mode in response to a reset signal applied to a reset terminal which is one of the connection terminals.

Abstract: A chip manufacturing method sets a first and a second section lines in parallel to each other along one side of each rectangular integrated circuit formed on a circuit substrate, and forms test wirings and test pads in gaps between the first and second section lines. After the circuit substrate is sectioned along the outer first section lines, a circuit test is conducted on resulting integrated circuits. After the circuit test is completed, a portion outside the second section line is cut away from each circuit chip. The test pads remain on circuit chips which are to undergo a circuit test, whereas no test pads remain on finished circuit chips which are to be shipped. It is therefore possible to prevent a user from fraudulently accessing the integrated circuit through the test pads of the circuit chip.

Abstract: A chip manufacturing method sets a first and a second section lines in parallel to each other along one side of each rectangular integrated circuit formed on a circuit substrate, and forms test wirings and test pads in gaps between the first and second section lines. After the circuit substrate is sectioned along the outer first section lines, a circuit test is conducted on resulting integrated circuits. After the circuit test is completed, a portion outside the second section line is cut away from each circuit chip. The test pads remain on circuit chips which are to undergo a circuit test, whereas no test pads remain on finished circuit chips which are to be shipped. It is therefore possible to prevent a user from fraudulently accessing the integrated circuit through the test pads of the circuit chip.

Abstract: In an error correcting system, an error correcting unit stores a subframe data sequentially and circularly in first to third subframe memories. The subframe data is supplied continuously and is subjected to a first row direction error detecting and correcting process. The error correcting unit performs a column direction error detecting and correcting process to first and second subframe data and then performs a second row direction error detecting and correcting process to a part of the first subframe data, while the first row direction error detecting and correcting process is performed to a third subframe data to store in the third subframe memory. Also, the error correcting unit performs the second row direction error detecting and correcting process to a remaining part of the first subframe data and the second subframe data, while the first row direction error detecting and correcting process is performed to a fourth subframe data to store in the first subframe memory from a head location.

Abstract: Received data is applied in units of blocks to an error correcting unit and a data holding unit. If the error correcting unit normally performs error correction, the output from the error correcting unit is stored in a frame buffer. If the error correcting unit does not normally perform error correction, the data in the data holding unit is stored in the frame buffer. In this manner the first error correction processing is performed. Bit data is sequentially read out in units of bits from each block stored in the frame buffer, subjected to the second error correction processing, and returned to the frame buffer. The third error correction processing is further performed for the data sequentially output in units of blocks from the frame buffer.