Patents by Inventor Kunihiko Ikuzaki
Kunihiko Ikuzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5808951Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: September 17, 1997Date of Patent: September 15, 1998Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 5732037Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: May 23, 1995Date of Patent: March 24, 1998Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 5689457Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: March 6, 1996Date of Patent: November 18, 1997Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 5448520Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed irk the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: September 15, 1994Date of Patent: September 5, 1995Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 5365478Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: February 9, 1994Date of Patent: November 15, 1994Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 5170374Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: April 7, 1992Date of Patent: December 8, 1992Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki
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Patent number: 4860255Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: August 9, 1988Date of Patent: August 22, 1989Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4709353Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: December 15, 1986Date of Patent: November 24, 1987Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4646267Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETS formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: April 22, 1986Date of Patent: February 24, 1987Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4636989Abstract: A dynamic random access memory, which is accessed in response to an address strobe signal, has an automatic refresh circuit which consists of a clock generator that generates refresh clock pulses when the address strobe signal is not produced, and an address counter that increments a refresh address by counting the refresh clock pulses. Information retained in memory cells is automatically refreshed by an operation of the automatic refresh circuit. The dynamic random access memory of this arrangement does not need a special external terminal for the refresh operation and an external circuit associated therewith. Thus, the random access memory of this arrangement constructs, in effect, a pseudo static random access memory.Type: GrantFiled: September 3, 1985Date of Patent: January 13, 1987Assignee: Hitachi, Ltd.Inventor: Kunihiko Ikuzaki
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Patent number: 4592022Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: July 19, 1985Date of Patent: May 27, 1986Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4549284Abstract: A dynamic random access memory, which is accessed in response to an address strobe signal, has an automatic refresh circuit which consists of a clock generator that generates refresh clock pulses when the address strobe signal is not produced, and an address counter that increments a refresh address by counting the refresh clock pulses. Information retained in memory cells is automatically refreshed by an operation of the automatic refresh circuit. The dynamic random access memory of this arrangement does not need a special external terminal for the refresh operation and an external circuit associated therewith. Thus, the random access memory of this arrangement constructs, in effect, a pseudo static random access memory.Type: GrantFiled: March 10, 1983Date of Patent: October 22, 1985Assignee: Hitachi, Ltd.Inventor: Kunihiko Ikuzaki
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Patent number: 4539658Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: August 8, 1984Date of Patent: September 3, 1985Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4472792Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: May 13, 1982Date of Patent: September 18, 1984Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4085458Abstract: In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of memory cells of the matrix and a reference potential to which gates the source electrodes of the information storing MOSFET's of the memory cells are connected. The clamping MOSFET has a lower threshold voltage than a row selecting MOSFET connected to the word line and clamps the word line when the word line is not selected, so that a delay in the read-out operation is eliminated or suppressed.Type: GrantFiled: May 26, 1976Date of Patent: April 18, 1978Assignee: Hitachi, Ltd.Inventors: Kunihiko Ikuzaki, Tsuneo Ito, Masamichi Ishihara, Takashi Sato