Patents by Inventor Kunihiko Iwamoto
Kunihiko Iwamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10622443Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: GrantFiled: July 20, 2016Date of Patent: April 14, 2020Assignee: ROHM CO., LTD.Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
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Patent number: 10566941Abstract: An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.Type: GrantFiled: July 25, 2018Date of Patent: February 18, 2020Assignee: ROHM CO., LTD.Inventors: Naohiro Nomura, Sachito Horiuchi, Kunihiko Iwamoto
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Patent number: 10554179Abstract: A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.Type: GrantFiled: August 6, 2018Date of Patent: February 4, 2020Assignee: ROHM CO., LTD.Inventors: Naohiro Nomura, Sachito Horiuchi, Kunihiko Iwamoto, Takatoshi Manabe
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Publication number: 20190052231Abstract: A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.Type: ApplicationFiled: August 6, 2018Publication date: February 14, 2019Inventors: Naohiro NOMURA, Sachito HORIUCHI, Kunihiko IWAMOTO, Takatoshi MANABE
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Publication number: 20190036500Abstract: An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.Type: ApplicationFiled: July 25, 2018Publication date: January 31, 2019Inventors: Naohiro NOMURA, Sachito HORIUCHI, Kunihiko IWAMOTO
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Publication number: 20160329399Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Applicant: ROHM CO., LTD.Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
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Patent number: 9425203Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: GrantFiled: June 10, 2015Date of Patent: August 23, 2016Assignee: ROHM CO., LTD.Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
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Publication number: 20150279848Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: ApplicationFiled: June 10, 2015Publication date: October 1, 2015Applicant: ROHM CO., LTD.Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
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Patent number: 9082654Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: GrantFiled: May 29, 2014Date of Patent: July 14, 2015Assignee: ROHM CO., LTD.Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
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Publication number: 20140353737Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: ApplicationFiled: May 29, 2014Publication date: December 4, 2014Applicant: ROHM CO., LTD.Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
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Patent number: 8367560Abstract: A semiconductor device manufacturing method includes the steps of forming a silicate film by performing a first step of forming a metal oxide film on a silicon substrate, and a second step of inducing a solid phase reaction between the metal oxide film and a surface of the silicon substrate by heat treatment, and forming a high dielectric constant insulating film on the silicate film.Type: GrantFiled: June 10, 2008Date of Patent: February 5, 2013Assignees: Hitachi Kokusai Electric Inc., Rohm Co., Ltd.Inventors: Arito Ogawa, Kunihiko Iwamoto, Hiroyuki Ota
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Patent number: 8207584Abstract: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.Type: GrantFiled: December 6, 2008Date of Patent: June 26, 2012Assignees: Renesas Electronics Corporation, Rohm Co., Ltd.Inventors: Toshihide Nabatame, Kunihiko Iwamoto, Yuuichi Kamimuta
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Patent number: 7884423Abstract: CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer 20, placed on the 1st gate insulating film 16, having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12); a second metal oxide layer 24; and a second metal oxide layer 24, the p-MISFETs including: a second gate insulating film 18 placed on the surface of the semiconductor substrate 10; a third metal oxide layer 22, placed on the 2nd gate insulating film 18, having a composition ratio shown with M3zM4wO (M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14); a fourth metal oxide layer 26; and a second conductive layer 30 placed on the fourth metal oxide layer 26.Type: GrantFiled: June 6, 2008Date of Patent: February 8, 2011Assignees: Rohm Co., Ltd., Hitachi Kokusai Electric Inc., Kabushiki Kaisha ToshibaInventors: Kunihiko Iwamoto, Arito Ogawa, Yuuichi Kamimuta
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Patent number: 7790627Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.Type: GrantFiled: December 11, 2007Date of Patent: September 7, 2010Assignee: Rohm Co., Ltd.Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
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Patent number: 7772678Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.Type: GrantFiled: December 12, 2008Date of Patent: August 10, 2010Assignees: Rohm Co., Ltd., Horiba, Ltd., Renesas Technology Corp.Inventors: Kunihiko Iwamoto, Koji Tominaga, Toshihide Nabatame, Tomoaki Nishimura
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Publication number: 20090146216Abstract: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.Type: ApplicationFiled: December 6, 2008Publication date: June 11, 2009Inventors: Toshihide NABATAME, Kunihiko IWAMOTO, Yuuichi KAMIMUTA
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Publication number: 20090096067Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film. Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.Type: ApplicationFiled: December 12, 2008Publication date: April 16, 2009Applicants: ROHM CO., LTD., HORIBA, LTD., RENESAS TECHNOLOGY CORP.,Inventors: Kunihiko IWAMOTO, Koji TOMINAGA, Toshihide NABATAME, Tomoaki NISHIMURA
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Patent number: 7482234Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.Type: GrantFiled: August 27, 2004Date of Patent: January 27, 2009Assignees: Rohm Co., Ltd., Horiba, Ltd., Renesas Technology Corp.Inventors: Kunihiko Iwamoto, Koji Tominaga, Toshihide Nabatame, Tomoaki Nishimura
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Publication number: 20080318442Abstract: The present invention has an object of providing a substrate processing apparatus and a semiconductor device manufacturing method that can prevent adverse effects on electrical characteristics and provide a thinner EOT. A semiconductor device manufacturing method comprises the steps of: forming a metal oxide film on a silicon substrate, and forming a silicate film by inducing a solid phase reaction between the metal oxide film and the silicon substrate by heat treatment, and forming a high dielectric constant insulating film on the silicate film.Type: ApplicationFiled: June 10, 2008Publication date: December 25, 2008Applicants: HITACHI KOKUSAI ELECTRIC INC., ROHM CO., LTD.Inventors: Arito Ogawa, Kunihiko Iwamoto, Hiroyuki Ota
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Publication number: 20080303099Abstract: CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer 20, placed on the 1st gate insulating film 16, having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12); a second metal oxide layer 24; and a second metal oxide layer 24, the p-MISFETs including: a second gate insulating film 18 placed on the surface of the semiconductor substrate 10; a third metal oxide layer 22, placed on the 2nd gate insulating film 18, having a composition ratio shown with M3zM4wO (M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14); a fourth metal oxide layer 26; and a second conductive layer 30 placed on the fourth metal oxide layer 26.Type: ApplicationFiled: June 6, 2008Publication date: December 11, 2008Applicants: Rohm Co., Ltd., Hitachi Kokusai Electric Inc., Kabushiki Kaisha ToshibaInventors: Kunihiko Iwamoto, Arito Ogawa, Yuuichi Kamimuta