Patents by Inventor Kunihiko Karasawa

Kunihiko Karasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6833590
    Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: December 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Chikao Makita, Kunihiko Karasawa
  • Publication number: 20030230781
    Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Application
    Filed: March 4, 2003
    Publication date: December 18, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Chikao Makita, Kunihiko Karasawa
  • Patent number: 6583475
    Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: June 24, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Chikao Makita, Kunihiko Karasawa
  • Publication number: 20020089018
    Abstract: The NMOS transistor circuit has the surge protection circuit connected in parallel with the NMOS transistor. Resistor is provided between back gate of the NMOS transistor and the ground. As a result, input impedance higher than input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Application
    Filed: June 4, 2001
    Publication date: July 11, 2002
    Inventors: Chikao Makita, Kunihiko Karasawa
  • Patent number: 5693934
    Abstract: Photocurrents outputted by photo detecting circuits (1.sub.1 to 1.sub.n) disposed in first current paths (2.sub.1 to 2.sub.n) are amplified by current amplifying means (3.sub.1 to 3.sub.n) disposed in the first current paths (2.sub.1 to 2.sub.n), respectively. The output currents from the plurality of current amplifying means (3.sub.1 to 3.sub.n) are converted into voltage all by one current-voltage converting means (5). The current amplifying means (3.sub.1 to 3.sub.n) are turned on or off by control signals (3.sub.1S to 3.sub.nS), and therefore the luminance detecting circuit amplifies the current of the required photo detecting element only, and outputs into the current-voltage converting means (5).
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: December 2, 1997
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.
    Inventors: Tatsuya Hohmoto, Hiroshi Murakami, Kunihiko Karasawa, Hideo Hara
  • Patent number: 5412559
    Abstract: The present invention is directed to a full wave rectifying circuit where a single input a.c. signal is used to perform full wave rectification with enhanced accuracy. An a.c. signal is transmitted from an a.c. signal source (1) via a coupling capacitor (3) to bases of transistors (Q1, Q4) of first and second differential gain stages (S1, S2). Outputs from the first and second differential gain stages (S1, S2) are received on input terminals of first and second current mirror circuits (K1, K2). Output currents (I.sub.011, I.sub.012) from the first and second current mirror circuits (K1, K2) are converted by load resistances working as current-voltage converting means, and then, output voltage V.sub.OUT1 rectified on the full wave basis is output from an output terminal (12). Portions of the a.c. signal out of phase from each other are rectified on the half wave basis by the first and second differential gain stages (S1, S2) and then they are added, so that a single input a.c.
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: May 2, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kunihiko Karasawa
  • Patent number: 4317845
    Abstract: One side surface of a continuous metal strip is continuously brought into contacted with a surface of a molten metal bath. The surface of the molten metal bath is flowed to the directions departing from both edges of the strip by a linear induction motor dipped in the bath. A one side surface metal coated product having no deposition of a molten metal on the reverse surface is obtained by the method of the present invention.
    Type: Grant
    Filed: April 1, 1980
    Date of Patent: March 2, 1982
    Assignees: Asahi Glass Co. Ltd., Nihon Parkerizing Co.
    Inventors: Kunihiko Karasawa, Tokushiro Hosoda, Hiroshi Mase, Yasuo Sato, Shoji Shimada