Abstract: Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element R1, and an Nch transistor N2, having as load a Pch transistor P2 and resistance element R2; and an Nch transistor N3 supplying operating current to the differential pair. The input/output terminal DQ is connected to the drain of the Nch transistor N1. The output stage is operated as differential pair, in the normal operation mode (TM=L), wherein the Pch transistors P1, P2 are ON, a read-data signal RD is supplied to the differential pair, and a specified voltage CC is supplied to the gate of the Nch transistor N3; and in the test mode (TM=H), a CMOS circuit is established wherein a read-data signal RD is supplied to the gate of the Pch transistor P1 and the gate of the Nch transistor N3, turning the Nch transistor N1 ON.

Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

Abstract: To use both an array of main memory cells and an array of redundant memory cells efficiently during a block writing operation, a memory system for performing the block writing operation includes a bit line activator activating at least one bit line of bit lines of the array of main memory cells and at least one bit line of bit lines of the array of redundant memory cells simultaneously during the block writing operation.

Abstract: A semiconductor memory device including redundancy decision circuitry having a block writing function is disclosed. The redundancy decision circuitry assigns a single fuse and a single transistor to each pair of upper and lower bits of a plurality of column addresses. Selectors each selects either one of particular upper and lower bits input thereto. The device therefore reduces the number of fuses corresponding to column mask signals to be used at the time of block writing, thereby reducing the area to be occupied by the redundancy decision circuitry.

Abstract: A cassette tape recorder (1) of pocket size, which is detachably coupled to a radio receiver (2) is given music searching function. The cassette tape recorder (1) is normally powered by small capacity cells (B1) when used by itself, and is powered by a large capacity power source (B2) included in the radio (2). A reproducing signal derived from a reproduce head (9) is fed to a solenoid control circuit (14) built in the radio (2) to detect a no-signal portion between two consecutive music pieces. When such a no-signal portion is detected during music search with fast playback, a solenoid driving signal is fed to a solenoid (12) built in the tape recorder (1) to terminate fast playback and put the tape recorder (1) in a normal playback mode. A switch (S1) arranged to be automatically switched when the tape recorder (1) engages the radio (2) is provided to automatically select the small or large capacity power source (B1 or B2).