Abstract: An electrode structure includes: a plurality of pixel electrodes arranged separately from each other; and a plurality of dielectric layers laminated in a first direction with respect to the plurality of pixel electrodes, in which the plurality of dielectric layers includes: a first dielectric layer that spreads over the plurality of pixel electrodes in a direction intersecting with the first direction; and a second dielectric layer that includes dielectric material having a refractive index higher than that of the first dielectric layer, sandwiches the first dielectric layer together with the plurality of pixel electrodes, and has a slit at a position overlapping space between pixel electrodes adjacent when viewed from the first direction.

Abstract: Input/output AC characteristics of a hard macro cell is specified in advance, delay cells 15 and 16 are provided in the input and output sides of the hard macro cell, and signal propagation delay times of the delay cells 15 and 16 are set so as to satisfy the specifications. These delay times are determined in such a way that no timing error occurs at the data inputs D of the D flip-flops 11 and 22 on condition that D flip-flops 20 and 22 are arranged outside the hard macro cell 10A, the data output end Q of the D flip-flop 20 is directly connected by a line to the data input end DI of the hard macro cell 10A, the data input end of the external synchronous flip-flop 22 is directly connected to the data output end DO of the hard macro cell 10A, and a clock CLK is commonly provided to the clock input ends CK of the hard macro cell 10A and the D flip-flops 20 and 22.

Abstract: A semiconductor integrated circuit device includes a preceding circuit portion, a flip-flop circuit portion receiving complementary output signals of the preceding circuit portion, for latching data in accordance with the complementary output signals of the preceding circuit portion, and a compensation circuit portion receiving complementary output signals of the flip-flop circuit portion and receiving the complementary output signals of the preceding circuit portion without passing through the flip-flop circuit portion, for compensating driving power and decreasing a delay time of a specific phase. Therefore, the delay time of the semiconductor integrated circuit device can be decreased in one phase (specific phase).