Abstract: A fractional frequency divider circuit includes: a frequency divider circuit configured to frequency-divide an input clock at 1/CTSquo, wherein the CTSquo is a quotient of CTS/N; a clock addition circuit configured to add one clock to an output of the frequency divider circuit; a counter that counts the number of cycles of the output of the frequency divider circuit by a carry of the frequency divider circuit or an output of the clock addition circuit; a match detection circuit that determines whether an integer multiple of N/CTSrem matches a value of the counter, wherein the CTSrem is a remainder of CTS/N; and a selector circuit that outputs the output of the clock addition circuit as an output clock when the match is detected by the match detection circuit, and outputs the output of the frequency divider circuit as an output clock when the match is not detected.

Abstract: A fractional frequency divider circuit includes: a frequency divider circuit configured to frequency-divide an input clock at 1/CTSquo, wherein the CTSquo is a quotient of CTS/N; a clock addition circuit configured to add one clock to an output of the frequency divider circuit; a counter that counts the number of cycles of the output of the frequency divider circuit by a carry of the frequency divider circuit or an output of the clock addition circuit; a match detection circuit that determines whether an integer multiple of N/CTSrem matches a value of the counter, wherein the CTSrem is a remainder of CTS/N; and a selector circuit that outputs the output of the clock addition circuit as an output clock when the match is detected by the match detection circuit, and outputs the output of the frequency divider circuit as an output clock when the match is not detected.

Abstract: A voltage control oscillator includes: a voltage-current converter circuit that converts an inputted voltage to a current according to the value of the voltage; a current mirror circuit; a ring oscillator including differential inverters connected in multiple stages; an inverting amplifier; and a buffer. The ring oscillator outputs, from each of the differential inverters, a signal amplitude-limited by a current converted by the voltage-current converter circuit and the current mirror circuit and a voltage applied from the inverting amplifier and the ring oscillator outputs an oscillatory frequency in response to the output signal.

Abstract: A voltage control oscillator according to the present invention includes: a voltage-current converter circuit that converts an inputted voltage to a current according to the value of the voltage; a current mirror circuit; a ring oscillator including differential inverters connected in multiple stages; an inverting amplifier; and a buffer. The ring oscillator outputs, from each of the differential inverters, a signal amplitude-limited by a “current converted by the voltage-current converter circuit and the current mirror circuit” and a “voltage applied from the inverting amplifier” and the ring oscillator outputs an oscillatory frequency in response to the output signal.

Abstract: A receiver for use in a system for transmission from a transmitter to a receiver, the receiver includes a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to a pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of a first natural number, the integral multiple of the first natural number being greater than or equal to 1; and a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock.

Abstract: A receiver for use in a system for transmission from a transmitter to a receiver is provided, the receiver including: a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to a pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of a first natural number, the integral multiple of the first natural number being greater than or equal to 1; and a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a secon