Patents by Inventor Kunihiko Nishimura
Kunihiko Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136439Abstract: A semiconductor device includes a substrate, a semiconductor layer, an element region, and fin transistors. The substrate includes a principal surface. The semiconductor layer is formed as a surface layer or on the principal surface of the substrate, the surface layer being the principal surface of the substrate. The semiconductor layer has a crystal structure in which an angle between two of crystal orientations with equivalent relationships on a crystal plane having a correspondence with the principal surface of the substrate is 60 degrees or 120 degrees. The element region includes unit element regions formed on the principal surface of the substrate. The fin transistors are formed in the semiconductor layer, in the respective unit element regions. The fin transistors radially extend from a center toward an outer periphery of the element region. Adjacent two of the fin transistors have a spacing with a 60° angle or a 120° angle.Type: ApplicationFiled: March 22, 2021Publication date: April 25, 2024Applicant: Mitsubishi Electric CorporationInventors: Yuki TAKIGUCHI, Eiji YAGYU, Kunihiko NISHIMURA, Hisashi SAITO, Takahiro YAMADA, Daisuke TSUNAMI, Marika NAKAMURA, Masanao ITO
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Patent number: 11961765Abstract: The present invention relates to a method for manufacturing a semiconductor substrate, including: (a) preparing an epitaxial substrate having a nitride semiconductor layer formed on a first main surface of a growth substrate and preparing a first support substrate, forming a resin adhesive layer between the first main surface of the growth substrate and a first main surface of the first support substrate, and bonding the epitaxial substrate to the first support substrate; (b) thinning a second main surface of the growth substrate; (c) forming a first protective thin film layer on the thinned growth substrate; (d) forming a second protective thin film layer on the first support substrate; (e) removing the thinned growth substrate; (f) bonding a second support substrate onto the nitride semiconductor layer; and (g) removing the first support substrate and the resin adhesive layer.Type: GrantFiled: May 23, 2019Date of Patent: April 16, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shuichi Hiza, Kunihiko Nishimura, Masahiro Fujikawa, Yuki Takiguchi, Eiji Yagyu
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Publication number: 20240096968Abstract: It is an object of the present disclosure to impart desired high frequency characteristics to a nitride semiconductor device including diamond as a substrate at a low cost. In the nitride semiconductor device according to the present disclosure, a via hole extends from a first main surface of a diamond layer through the diamond layer, an intermediate layer, and a nitride semiconductor layer to an electrode. The via hole has a multi-step structure including a large-diameter via hole being in contact with the first main surface of the diamond layer and a small-diameter via hole facing the electrode, having a smaller diameter than the large-diameter via hole, and being tapered.Type: ApplicationFiled: February 17, 2021Publication date: March 21, 2024Applicant: Mitsubishi Electric CorporationInventors: Ken IMAMURA, Shuichi HIZA, Kunihiko NISHIMURA
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Publication number: 20240030055Abstract: A nitride semiconductor layer formed on a growth substrate is attached to a support substrate via a reversible adhesive layer. Next, the growth substrate is removed, a new substrate is bonded to the exposed nitride semiconductor layer, and subsequently, the reversible adhesive layer and the support substrate are removed. As a result, the nitride semiconductor layer is transferred on the new substrate from the growth substrate. Performed in a step of bonding the nitride semiconductor layer and the new substrate are a step of pressure-contacting the nitride semiconductor layer and the new substrate, a step of softening the reversible adhesive layer, and a step of curing the reversible adhesive layer again.Type: ApplicationFiled: February 4, 2021Publication date: January 25, 2024Applicant: Mitsubishi Electric CorporationInventors: Shuichi HIZA, Kunihiko NISHIMURA
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Patent number: 11854856Abstract: An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.Type: GrantFiled: February 25, 2019Date of Patent: December 26, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Masahiro Fujikawa, Kunihiko Nishimura, Shuichi Hiza, Eiji Yagyu
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Publication number: 20230290635Abstract: A provided is a polycrystalline diamond substrate that can reduce the cost for inhibiting warpage. The polycrystalline diamond substrate is a polycrystalline diamond substrate having a first principal surface and a second principal surface, and includes, between the first principal surface and the second principal surface, a surface having an average grain diameter smaller than each of average grain diameters of the first principal surface and the second principal surface.Type: ApplicationFiled: September 18, 2020Publication date: September 14, 2023Applicant: Mitsubishi Electric CorporationInventors: Ken IMAMURA, Masahiro FUJIKAWA, Kunihiko NISHIMURA, Eiji YAGYU
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Publication number: 20230238296Abstract: A split in a dicing street in a semiconductor film is prevented. A semiconductor device includes: a first dicing street passing between a plurality of element regions on which a plurality of protective films are formed one-to-one, the first dicing street extending along a first axis; a second dicing street passing between the plurality of element regions and extending along a second axis; and a stop island disposed on the upper surface of the semiconductor film at an intersection between the first dicing street and the second dicing street, the stop island being in non-contact with the plurality of element regions. X_si>X_ds and Y_si<Y_ds are satisfied.Type: ApplicationFiled: May 25, 2020Publication date: July 27, 2023Applicant: Mitsubishi Electric CorporationInventors: Kunihiko NISHIMURA, Masahiro FUJIKAWA, Shuichi HIZA, Shinya NISHIMURA, Ken IMAMURA, Yuki TAKIGUCHI, Eiji YAGYU
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Publication number: 20230155351Abstract: A semiconductor device includes a first substrate, a semiconductor layer consisting of a nitride-based compound semiconductor, and a bonding layer bonded to the first substrate and the semiconductor layer between the first substrate and the semiconductor layer, and containing at least one of constituent elements of the nitride-based compound semiconductor.Type: ApplicationFiled: May 14, 2020Publication date: May 18, 2023Applicant: Mitsubishi Electric CorporationInventors: Shinya NISHIMURA, Shuichi HIZA, Kunihiko NISHIMURA, Eiji YAGYU
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Publication number: 20230120994Abstract: The present disclosure relates to a semiconductor substrate manufacturing method including: forming a catalytic metal film composed of a transition metal on a main surface to be polished of a workpiece substrate composed of any one of diamond, silicon carbide, gallium nitride, and sapphire; and providing relative movement between the workpiece substrate on which the catalytic metal film has been formed and a polishing platen in an oxidant solution to remove a compound generated by chemical reaction of an active radical generated by reaction of the catalytic metal film and the oxidant solution and a surface atom on the main surface of the workpiece substrate to thereby polish the workpiece substrate. The manufacturing method further includes: bonding the polished workpiece substrate to a nitride semiconductor layer by room temperature bonding; and removing a support substrate and a resin adhesive layer.Type: ApplicationFiled: April 3, 2020Publication date: April 20, 2023Applicant: Mitsubishi Electric CorporationInventors: Shuichi HIZA, Kunihiko NISHIMURA, Yuki TAKIGUCHI, Eiji YAGYU
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Publication number: 20220314357Abstract: Removal of substrates in a composite substrate is facilitated, and flaking of the composite substrate in an unintended process is prevented. A method for manufacturing a composite substrate includes: forming a first bonding material in a first surface of a first substrate; forming, in the first surface, at least one groove located more inward than a periphery in a plan view of the first substrate; forming the first bonding material along an inner wall of the at least one groove, the first bonding material not filling into space enclosed by the inner wall of the at least one groove; forming a second bonding material on a second surface of a second substrate; and bonding the first bonding material and the second bonding material together in a region except the at least one groove.Type: ApplicationFiled: June 21, 2019Publication date: October 6, 2022Applicant: Mitsubishi Electric CorporationInventors: Kunihiko NISHIMURA, Keisuke NAKAMURA, Masahiro FUJIKAWA, Shuichi HIZA, Tomohiro SHINAGAWA, Eiji YAGYU
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Publication number: 20220230920Abstract: The present invention relates to a method for manufacturing a semiconductor substrate, including: (a) preparing an epitaxial substrate having a nitride semiconductor layer formed on a first main surface of a growth substrate and preparing a first support substrate, forming a resin adhesive layer between the first main surface of the growth substrate and a first main surface of the first support substrate, and bonding the epitaxial substrate to the first support substrate; (b) thinning a second main surface of the growth substrate; (c) forming a first protective thin film layer on the thinned growth substrate; (d) forming a second protective thin film layer on the first support substrate; (e) removing the thinned growth substrate; (0 bonding a second support substrate onto the nitride semiconductor layer; and (g) removing the first support substrate and the resin adhesive layer.Type: ApplicationFiled: May 23, 2019Publication date: July 21, 2022Applicant: Mitsubishi Electric CorporationInventors: Shuichi HIZA, Kunihiko NISHIMURA, Masahiro FUJIKAWA, Yuki TAKIGUCHI, Eiji YAGYU
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Publication number: 20220059386Abstract: An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.Type: ApplicationFiled: February 25, 2019Publication date: February 24, 2022Applicant: Mitsubishi Electric CorporationInventors: Masahiro FUJIKAWA, Kunihiko NISHIMURA, Shuichi HIZA, Eiji YAGYU
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Patent number: 11107685Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.Type: GrantFiled: February 1, 2018Date of Patent: August 31, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Keisuke Nakamura, Muneyoshi Suita, Akifumi Imai, Kenichiro Kurahashi, Tomohiro Shinagawa, Takashi Matsuda, Koji Yoshitsugu, Eiji Yagyu, Kunihiko Nishimura
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Patent number: 10622532Abstract: A thermoelectric conversion module includes a plurality of thermoelectric conversion elements formed on a first main surface of an inner tube, and a plurality of projections formed on a second main surface of an outer tube. The thermoelectric conversion element includes an interconnection, and an electrode formed at a first distance from the second main surface in a second direction. When the thermoelectric conversion module is seen from a first direction, the projections include a first projection and a second projection formed at a spacing therebetween in a third direction. A shortest distance between a first lateral surface and a top portion of the first projection and a shortest distance between a second lateral surface and a top portion of the second projection are smaller than the first distance.Type: GrantFiled: December 9, 2016Date of Patent: April 14, 2020Assignee: Mitsubishi Electric CorporationInventors: Akira Yamashita, Hidetada Tokioka, Takayuki Morioka, Kunihiko Nishimura, Shinya Nishimura, Mutsumi Tsuda
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Publication number: 20200028048Abstract: A thermoelectric conversion module includes a plurality of thermoelectric conversion elements formed on a first main surface of an inner tube, and a plurality of projections formed on a second main surface of an outer tube. The thermoelectric conversion element includes an interconnection, and an electrode formed at a first distance from the second main surface in a second direction. When the thermoelectric conversion module is seen from a first direction, the projections include a first projection and a second projection formed at a spacing therebetween in a third direction. A shortest distance between a first lateral surface and a top portion of the first projection and a shortest distance between a second lateral surface and a top portion of the second projection are smaller than the first distance.Type: ApplicationFiled: December 9, 2016Publication date: January 23, 2020Applicant: Mitsubishi Electric CorporationInventors: Akira YAMASHITA, Hidetada TOKIOKA, Takayuki MORIOKA, Kunihiko NISHIMURA, Shinya NISHIMURA, Mutsumi TSUDA
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Publication number: 20190362974Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.Type: ApplicationFiled: February 1, 2018Publication date: November 28, 2019Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Keisuke NAKAMURA, Muneyoshi SUITA, Akifumi IMAI, Kenichiro KURAHASHI, Tomohiro SHINAGAWA, Takashi MATSUDA, Koji YOSHITSUGU, Eiji YAGYU, Kunihiko NISHIMURA
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Publication number: 20170330990Abstract: A method for manufacturing a photovoltaic device capable of suppressing decreases in an open-circuit voltage and a fill factor or suppressing the occurrence of a current leak. The method for manufacturing a photovoltaic device includes: (a) forming a pyramidal texture on a first main surface of a silicon substrate; (b) forming a first silicate glass on the first main surface; (c) forming a second silicate glass on the first silicate glass; (d) diffusing the impurities of the first conductivity type contained in the first silicate glass to the first main surface of the silicon substrate; (e) forming a third silicate glass on the second silicate glass; and (f) diffusing impurities of a second conductivity type to a second main surface of the silicon substrate after (e).Type: ApplicationFiled: May 11, 2015Publication date: November 16, 2017Applicant: Mitsubishi Electric CorporationInventors: Takehiko SATO, Kunihiko NISHIMURA, Shinya NISHIMURA, Tatsuro WATAHIKI
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Patent number: 9051976Abstract: A hybrid driving force transmission device includes a motor generator (9), a multi-plate dry clutch (7), a housing cover (60), a dust seal member (62), and a dust collection structure (63). The multi-plate dry clutch (7) is disposed at a position inner than the motor generator (9). The housing cover (60) is provided to cover the motor generator (9) and the multi-plate dry clutch (7), and divides the internal space into a clutch chamber (64) and a motor chamber (65). The dust seal member (62) is disposed at a position radially outside of a clutch chamber open surface (66) and seals between a rotor (92) and an inner wall (60a) of the housing cover (60). The dust collection structure (63) forms a dust collection space (69) in a region radially between the seal surface (68) formed by the dust seal member (62) and the clutch chamber open surface (66).Type: GrantFiled: May 17, 2011Date of Patent: June 9, 2015Assignee: NISSAN MOTOR CO., LTD.Inventors: Takashi Kuwahara, Tomoharu Fuji, Shigeru Ishii, Tatsuya Osone, Kunihiko Nishimura
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Publication number: 20140308775Abstract: A photovoltaic power device includes a P-type silicon substrate, a low-resistance N-type diffusion layer diffused with an N-type impurity in a first concentration formed at a light-incidence surface side, grid electrodes formed on the low-resistance N-type diffusion layer, a P+ layer formed on a back surface, and a back surface electrode formed on the P+ layer. The photovoltaic power device has concave portions provided at a predetermined interval to reach the silicon substrate from an upper surface of the low-resistance N-type diffusion layer, and an upper surface of a region between adjacent concave portions includes the low-resistance N-type diffusion layer. A high-resistance N-type diffusion layer diffused with an N-type impurity in a second concentration, which is lower than the first concentration, is formed in a range of a predetermined depth from a formation surface of the concave portions.Type: ApplicationFiled: June 25, 2014Publication date: October 16, 2014Applicant: Mitsubishi Electric CorporationInventors: Takashi Ishihara, Kunihiko Nishimura
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Patent number: 8835333Abstract: A heat treatment method of the present invention includes mounting a plurality of semiconductor wafers upright on a treatment boat in parallel to each other, inserting the treatment boat in a space above an injector located in a tube to be oriented to plane surfaces of the semiconductor wafers in parallel to an extending direction of the tube, and heating the tube while continuously supplying source gas into the tube through openings of the injector.Type: GrantFiled: November 27, 2012Date of Patent: September 16, 2014Assignee: Mitsubishi Electric CorporationInventors: Narihito Ota, Kunihiko Nishimura