Patents by Inventor Kunihiko Tajiri
Kunihiko Tajiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972991Abstract: A semiconductor device includes: an inner frame that surrounds an outer circumference of a semiconductor chip; and an outer frame that surrounds an outer circumference of the inner frame; wherein the outer frame is configured with an exterior wall that surrounds the outer circumference of the inner frame, and a fibrous reinforcing member that is wound on an outer circumference of the exterior wall. This prevents the broken pieces of a component that constitutes the semiconductor device from being scattered outside the semiconductor device, thereby not only to achieve improvement in the reliability of the entire system, but also to achieve downsizing of the semiconductor device.Type: GrantFiled: February 1, 2019Date of Patent: April 30, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Hiroki Shiota, Tetsuo Motomiya, Kunihiko Tajiri, Jun Okada, Hiroumi Yamada, Kazutake Kadowaki
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Publication number: 20230271579Abstract: A power conversion apparatus includes a hermetic housing, a power semiconductor module, and dry gas. The hermetic housing includes a gas inlet valve and a gas outlet valve. The power semiconductor module is arranged in an internal space in the hermetic housing. The internal space in the hermetic housing is filled with dry gas.Type: ApplicationFiled: September 7, 2020Publication date: August 31, 2023Applicant: Mitsubishi Electric CorporationInventors: Junichi NAKASHIMA, Kenji FUJIWARA, Kozo HARADA, Kunihiko TAJIRI, Yuji SHIRAKATA
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Publication number: 20220084899Abstract: A semiconductor device includes: an inner frame that surrounds an outer circumference of a semiconductor chip; and an outer frame that surrounds an outer circumference of the inner frame; wherein the outer frame is configured with an exterior wall that surrounds the outer circumference of the inner frame, and a fibrous reinforcing member that is wound on an outer circumference of the exterior wall. This prevents the broken pieces of a component that constitutes the semiconductor device from being scattered outside the semiconductor device, thereby not only to achieve improvement in the reliability of the entire system, but also to achieve downsizing of the semiconductor device.Type: ApplicationFiled: February 1, 2019Publication date: March 17, 2022Applicant: Mitsubishi Electric CorporationInventors: Hiroki SHIOTA, Tetsuo MOTOMIYA, Kunihiko TAJIRI, Jun OKADA, Hiroumi YAMADA, Kazutake KADOWAKI
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Patent number: 8554819Abstract: A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit.Type: GrantFiled: August 7, 2009Date of Patent: October 8, 2013Assignee: Fujitsu LimitedInventor: Kunihiko Tajiri
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Patent number: 8392491Abstract: A shift calculator including a first shifter includes a right shifter configured to perform a right shift of 0 to 3 bits and a left shifter configured to perform a left shift of 0 to 3 bits, on input data of which a data width is N bits, in accordance with left/right selection signals, based on a shift amount of 3 bits or smaller out of an input shift amount, a rotator configured to perform a right rotate shift of 0 to N?4 bits or a left rotate shift of 0 to N?4 bits, on output data from said first shifter, in accordance with said left/right selection signals, based on a shift amount of 4 bits or greater out of the input shift amount, and a mask unit configured to perform mask processing in 4-bit increments on output data from said rotator based on mask signals.Type: GrantFiled: June 30, 2010Date of Patent: March 5, 2013Assignee: Fujitsu LimitedInventor: Kunihiko Tajiri
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Publication number: 20110004643Abstract: A shift calculator including a first shifter includes a right shifter configured to perform a right shift of 0 to 3 bits and a left shifter configured to perform a left shift of 0 to 3 bits, on input data of which a data width is N bits, in accordance with left/right selection signals, based on a shift amount of 3 bits or smaller out of an input shift amount, a rotator configured to perform a right rotate shift of 0 to N?4 bits or a left rotate shift of 0 to N?4 bits, on output data from said first shifter, in accordance with said left/right selection signals, based on a shift amount of 4 bits or greater out of the input shift amount, and a mask unit configured to perform mask processing in 4-bit increments on output data from said rotator based on mask signals.Type: ApplicationFiled: June 30, 2010Publication date: January 6, 2011Applicant: FUJITSU LIMITEDInventor: Kunihiko TAJIRI
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Patent number: 7720899Abstract: An arithmetic operation unit, which generates information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit outputting the arithmetic operation result, a normalizer having a plurality of shifter normalizing the arithmetic operation result, a shift amount calculator calculating a plurality of shift amounts for the plural shifter, and a predictor generating interim information that is a result of prediction of whether or not the arithmetic operation result is to be shifted when the arithmetic operation result is normalized, by using the plural shift amounts, and a generator generating the information by using the interim information. The cycle time required to generate a sticky bit is shortened to efficiently generate the sticky bit, and the hardware resources for generating the sticky bit is reduced.Type: GrantFiled: March 22, 2006Date of Patent: May 18, 2010Assignee: Fujitsu LimitedInventor: Kunihiko Tajiri
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Publication number: 20090300087Abstract: A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit.Type: ApplicationFiled: August 7, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventor: Kunihiko Tajiri
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Publication number: 20070130242Abstract: An arithmetic operation unit, which generates information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit outputting the arithmetic operation result, a normalizer having a plurality of shifter normalizing the arithmetic operation result, a shift amount calculator calculating a plurality of shift amounts for the plural shifter, and a predictor generating interim information that is a result of prediction of whether or not the arithmetic operation result is to be shifted when the arithmetic operation result is normalized, by using the plural shift amounts, and a generator generating the information by using the interim information. The cycle time required to generate a sticky bit is shortened to efficiently generate the sticky bit, and the hardware resources for generating the sticky bit is reduced.Type: ApplicationFiled: March 22, 2006Publication date: June 7, 2007Applicant: Fujitsu LimitedInventor: Kunihiko Tajiri