Abstract: According to one embodiment, a DRAM controller includes a clock generating and switching unit for supplying a first clock to a DRAM in a normal operation and generating a second clock having a lower speed than the first clock and supplying the generated second clock to the DRAM in an initialization processing, and a DRAM access circuit having a DLL circuit for regulating a fetch timing of data output from the DRAM based on the first clock, and fetching, in a fetch timing regulated by the DLL circuit, data output from the DRAM in a timing based on the second clock in relation to the initialization processing and the transfer data output from the DRAM in a timing based on the first clock in the initialization processing and the normal processing, respectively.

Abstract: A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

Abstract: An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories, and a memory controller controlling data transfer between the data processor and the plurality of memories. The memory controller includes an address calculation circuit calculating a second data address from a first data address included in the data access request, and a control unit controlling operation of the first and the second memory group by transmitting a first and a second control command in different clock cycles.

Abstract: An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories, and a memory controller controlling data transfer between the data processor and the plurality of memories. The memory controller includes an address calculation circuit calculating a second data address from a first data address included in the data access request, and a control unit controlling operation of the first and the second memory group by transmitting a first and a second control command in different clock cycles.

Abstract: A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

Abstract: A memory controller includes a state generator configured to generate a plurality of state information signals in response to command requests associated with a plurality of banks in a memory. An enable signal generator is configured to generate a plurality of enable signals indicating whether the state information signals are valid or invalid. A bank controller is configured to generate a command based on the state information signals and the enable signals.

Abstract: A memory controller includes a state generator configured to generate a plurality of state information signals in response to command requests associated with a plurality of banks in a memory. An enable signal generator is configured to generate a plurality of enable signals indicating whether the state information signals are valid or invalid. A bank controller is configured to generate a command based on the state information signals and the enable signals.

Abstract: The correlation between a coded block on the screen of the current image and a plurality of candidate blocks which exist in a search area on a reference screen temporally different from the current image and which has the same area as that of the coded block is obtained to select a candidate block having the highest correlation to obtain its displacement as a primary motion vector. Then, the positional relationship between a motion vector/corresponding candidate block and the reference screen is estimated to determine whether the search area/candidate block is positioned inside of the boundary of the reference screen. When a part of the search area/candidate block is positioned outside of the boundary, the position of the primary motion vector so that the search area/candidate block is located inside of the boundary of the reference.

Abstract: The correlation between a coded block on the screen of the current image and a plurality of candidate blocks which exist in a search area on a reference screen temporally different from the current image and which has the same area as that of the coded block is obtained to select a candidate block having the highest correlation to obtain its displacement as a primary motion vector. Then, the positional relationship between a motion vector/corresponding candidate block and the reference screen is estimated to determine whether the search area/candidate block is positioned inside of the boundary of the reference screen. When a part of the search area/candidate block is positioned outside of the boundary, the position of the primary motion vector so that the search area/candidate block is located inside of the boundary of the reference.