Abstract: A power supply apparatus supplies a power supply voltage VDD. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal VS that corresponds to the power supply voltage VDD. The compensation circuit has input/output characteristics fIO that correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current iCOMP that corresponds to the detection signal VS to or otherwise from a node for generating the power supply voltage VDD.

Abstract: This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.

Abstract: A power supply apparatus supplies a power supply voltage VDD. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal VS that corresponds to the power supply voltage VDD. The compensation circuit has input/output characteristics fIO that correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current iCOMP that corresponds to the detection signal VS to or otherwise from a node for generating the power supply voltage VDD.

Abstract: This embodiment relates to a clock data recovering apparatus capable of improving CID resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.

Abstract: A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Abstract: Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result.

Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.

Abstract: A clock data recovery device 1 generates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector 10, a phase delay unit 20, a time measurement unit 30, a phase selector 40, an edge detector 50, a polarity detector 60, a logic inverter 70, and a data output unit 80. The signal selector 10, the phase delay unit 20, the time measurement unit 30, and the phase selector 40 constitute a clock-generation device 1A. The phase delay unit 20 includes a plurality of cascaded delay elements 211 to 21P. The phase selector 40 selects a signal output from the delay element in a position corresponding to a unit interval time among the delay elements 211 to 21P, and outputs the signal as a feedback clock Feedback Clock.

Abstract: A clock data recovery device 1 generates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector 10, a phase delay unit 20, a time measurement unit 30, a phase selector 40, an edge detector 50, a polarity detector 60, a logic inverter 70, and a data output unit 80. The signal selector 10, the phase delay unit 20, the time measurement unit 30, and the phase selector 40 constitute a clock-generation device 1A. The phase delay unit 20 includes a plurality of cascaded delay elements 211 to 21P. The phase selector 40 selects a signal output from the delay element in a position corresponding to a unit interval time among the delay elements 211 to 21P, and outputs the signal as a feedback clock Feedback Clock.

Abstract: Provided is a measurement apparatus that measures an input signal, comprising a plurality of first comparators that each receive the input signal, have a common first reference level set therein, and compare a signal level of the input signal to the first reference level; and a level-crossing timing detecting section that detects a level-crossing timing at which the signal level crosses the first reference level, based on comparison results of the first comparators.

Abstract: Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result.

Abstract: Provided is a measurement apparatus that measures an input signal, comprising a plurality of first comparators that each receive the input signal, have a common first reference level set therein, and compare a signal level of the input signal to the first reference level; and a level-crossing timing detecting section that detects a level-crossing timing at which the signal level crosses the first reference level, based on comparison results of the first comparators.

Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.

Abstract: A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Abstract: There are provided a display apparatus and a display method, with which compressed image data that is to be decompressed can be transmitted to the display apparatus in an environment in which a transmission capacity is not always secured, and good image display is realized. An example of the display apparatus is an active matrix display apparatus formed by using thin-film transistors formed on an insulating substrate. In the active matrix display apparatus, a circuit that receives an image data signal from an external system via a non-contact transmission path and amplifies the image data signal, a circuit that processes the image data signal, and a memory circuit that stores the processed image data are integrated on the insulating substrate.

Abstract: There are provided a display apparatus and a display method, with which compressed image data that is to be decompressed can be transmitted to the display apparatus in an environment in which a transmission capacity is not always secured, and good image display is realized. An example of the display apparatus is an active matrix display apparatus formed by using thin-film transistors formed on an insulating substrate. In the active matrix display apparatus, a circuit that receives an image data signal from an external system via a non-contact transmission path and amplifies the image data signal, a circuit that processes the image data signal, and a memory circuit that stores the processed image data are integrated on the insulating substrate.

Abstract: There are provided a display apparatus and a display method, with which compressed image data that is to be decompressed can be transmitted to the display apparatus in an environment in which a transmission capacity is not always secured, and good image display is realized. An example of the display apparatus is an active matrix display apparatus formed by using thin-film transistors formed on an insulating substrate. In the active matrix display apparatus, a circuit that receives an image data signal from an external system via a non-contact transmission path and amplifies the image data signal, a circuit that processes the image data signal, and a memory circuit that stores the processed image data are integrated on the insulating substrate.

Abstract: Described are method and apparatus for protecting content of a semiconductor non-volatile memory and a semiconductor non-volatile memory itself, the semiconductor non-volatile memory being constituted by, for example, a flash memory, so that a reduction in a life time of the non-volatile memory due to an excess number of times a refresh (rewrite) operation can be prevented. For example, a first data deterioration determining voltage V.sub.1 is applied via a row decoder to one of word lines to which a selected bit is connected to determine whether the selected bit is turned on and a second data deterioration determining voltage V.sub.2 is applied to the same word line to determine whether the selected bit is turned off. The results of the determinations are stored in a second memory unit.