Abstract: A verification method is provided for verifying a semiconductor integrated circuit having a first logic macro-cell to be verified (101) and a plurality of second logic macro-cells (102-104) in which an output from the first logic macro-cell is inputted. The method sets a conversion slew rate Tmax that is a slew rate of a signal converted from a maximum allowable load of the first logic macro-cell. Input slew rates T1-T3 of signals that are inputted from the first logic macro-cell (101) to the second logic macro-cells (102-104) are obtained. The conversion slew rate Tmax is compared with each of the input slew rates T1-T3, and comparison results thereof are outputted. In this instance, an error is outputted when any one of the input slew rates T1-T3 exceeds the conversion slew rate Tmax.