Abstract: An image processing apparatus includes a memory unit configured to store original image data, a read unit configured to read, from the memory unit, image data of a rectangular area that is part of the original image data, to set pixel values to a flanking area that is added to the rectangular area in a surrounding space thereof, and to output extended image data inclusive of the image data of the rectangular area and image data of the flanking area to which the pixel values are set, and a first filtering process unit configured to apply a filtering process to the extended image data.

Abstract: An image processing apparatus includes a memory unit configured to store original image data, a read unit configured to read, from the memory unit, image data of a rectangular area that is part of the original image data, to set pixel values to a flanking area that is added to the rectangular area in a surrounding space thereof, and to output extended image data inclusive of the image data of the rectangular area and image data of the flanking area to which the pixel values are set, and a first filtering process unit configured to apply a filtering process to the extended image data.

Abstract: Aspects of an embodiment include providing a correction circuit that corrects image data in apiece of a frame, the correction circuit comprising: a weight processing unit which performs weighting on position data corresponding to a relative position in response to the relative position between a position of a pixel in the image data and a certain position in the frame; and a correction processing unit that corrects the image data based on a correction value corresponding to the weighted position data.

Abstract: An object of the present invention is to provide an image data processing circuit and an image data processing method capable of determining a reference signal level corresponding to black in an image with high precision by suppressing occurrence of line dependency and the like in a dark current component signal included in image data output from a solid state image pickup device. A reference dark current component data holding unit selects a reference line from a solid state image pickup device and holds a dark current component of the reference line as a head line average value. To a subtraction circuit, dark current component data and effective pixel data is sequentially input on the line unit basis. A differential circuit obtains, as a detection value, a change amount with respect to the head line average value, of the dark current component data included in a preceding line. The subtraction circuit subtracts the detection value from the dark current component data and the effective pixel data entered.

Abstract: A shading compensation circuit is provided which is capable of storing correction coefficients for shading compensation having optimal bit lengths, so that the data size of the correction coefficients can be reduced. The shading compensation circuit 10 for correcting the shading properties with respect to a horizontal direction and a vertical direction, has horizontal correction coefficient HHK and vertical correction coefficient VHK each having a bit length optimized according to a horizontal direction counter value HCT or a vertical direction counter value VCT. The horizontal and vertical correction coefficients HHK, VHK for the periphery of the image data are longer in bit length than the correction coefficients HHK, VHK for the center of the image data.

Abstract: An object is to provide an image processing circuit and an image processing method which can use various technologies for a bayer array CCD even when an RGB independent array CCD is used, and can accommodate for the bayer array CCD. A first matrix acquiring circuit 21G acquires an R signal for each basic matrix, and a first averaging circuit 31G outputs an average value AveCH1 of the R signal. Similarly, a second matrix acquiring circuit 22G acquires a G signal, and a second averaging circuit 32G outputs an average value AveCH2 of the G signal. Further, similarly, a third matrix acquiring circuit 23G acquires a B signal, and a third averaging circuit 33G outputs an average value AveCH3 of the B signal. A data array conversion circuit 40G converts the average values AveCH1 through AveCH3 into a conversion matrix of two pixels×two pixels in bayer array. The conversion matrix is detected by a detection circuit 70 for bayer array.

Abstract: A serial data receiving circuit and a serial data receiving method are provided which are capable of performing interconversion on bit sequences of data bit groups, between LSB first and MSB first, in serial data transmitted serially in successive data bit groups. Conversion parts C1 through C8 receive 8 different bit strings BS1 through BS8 having a 32-bit bit length and in which a start position of a head bit is shifted by one bit at a time. Conversion parts C1 through C8 perform a conversion operation to reverse a bit sequence of the bit strings BS1 through BS8 every 8 bits starting from a head bit. Coincidence detection circuits D1 through D8 perform coincidence detection on the bit strings BS1 through BS8 to detect coincidence with a synchronization pattern RS. A selector circuit 60 extracts any of upper bit strings HCBS1 through HCBS8 from the bit strings on which coincidence detection was performed, and outputs the result as detection data FD.

Abstract: Aspects of an embodiment include providing a correction circuit that corrects image data in a piece of a frame, the correction circuit comprising: a weight processing unit which performs weighting on position data corresponding to a relative position in response to the relative position between a position of a pixel in the image data and a certain position in the frame; and a correction processing unit that corrects the image data based on a correction value corresponding to the weighted position data.

Abstract: A table value conversion device for use with a memory in which a default table value is stored, a central processing unit for reading a default table value from the memory and outputting an output value, and a functional macro functioning as hardware for processing data and storing a lookup table. The device enables simple and efficient rewriting of values stored in the memory. The device includes a conversion module arranged on an external bus extending between the memory and the central processing unit. The conversion module receives the output value of the central processing unit, performs a correction computation on the received output value to generate a corrected value, and converts a table value of the lookup table in the functional macro based on the corrected value.

Abstract: A serial data receiving circuit and a serial data receiving method are provided which are capable of performing interconversion on bit sequences of data bit groups, between LSB first and MSB first, in serial data transmitted serially in successive data bit groups. Conversion parts C1 through C8 receive 8 different bit strings BS1 through BS8 having a 32-bit bit length and in which a start position of a head bit is shifted by one bit at a time. Conversion parts C1 through C8 perform a conversion operation to reverse a bit sequence of the bit strings BS1 through BS8 every 8 bits starting from a head bit. Coincidence detection circuits D1 through D8 perform coincidence detection on the bit strings BS1 through BS8 to detect coincidence with a synchronization pattern RS. A selector circuit 60 extracts any of upper bit strings HCBS1 through HCBS8 from the bit strings on which coincidence detection was performed, and outputs the result as detection data FD.

Abstract: A shading compensation circuit is provided which is capable of storing correction coefficients for shading compensation having optimal bit lengths, so that the data size of the correction coefficients can be reduced. The shading compensation circuit 10 for correcting the shading properties with respect to a horizontal direction and a vertical direction, has horizontal correction coefficient HHK and vertical correction coefficient VHK each having a bit length optimized according to a horizontal direction counter value HCT or a vertical direction counter value VCT. The horizontal and vertical correction coefficients HHK, VHK for the periphery of the image data are longer in bit length than the correction coefficients HHK, VHK for the center of the image data.

Abstract: An object of the present invention is to provide an image data processing circuit and an image data processing method capable of determining a reference signal level corresponding to black in an image with high precision by suppressing occurrence of line dependency and the like in a dark current component signal included in image data output from a solid state image pickup device. A reference dark current component data holding unit selects a reference line from a solid state image pickup device and holds a dark current component of the reference line as a head line average value. To a subtraction circuit, dark current component data and effective pixel data is sequentially input on the line unit basis. A differential circuit obtains, as a detection value, a change amount with respect to the head line average value, of the dark current component data included in a preceding line. The subtraction circuit subtracts the detection value from the dark current component data and the effective pixel data entered.

Abstract: An object is to provide an image processing circuit and an image processing method which can use various technologies for a bayer array CCD even when an RGB independent array CCD is used, and can accommodate for the bayer array CCD. A first matrix acquiring circuit 21G acquires an R signal for each basic matrix, and a first averaging circuit 31G outputs an average value AveCH1 of the R signal. Similarly, a second matrix acquiring circuit 22G acquires a G signal, and a second averaging circuit 32G outputs an average value AveCH2 of the G signal. Further, similarly, a third matrix acquiring circuit 23G acquires a B signal, and a third averaging circuit 33G outputs an average value AveCH3 of the B signal. A data array conversion circuit 40G converts the average values AveCH1 through AveCH3 into a conversion matrix of two pixels×two pixels in bayer array. The conversion matrix is detected by a detection circuit 70 for bayer array.

Abstract: A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Abstract: A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Abstract: A bus controller for a CCD digital still camera arbitrates competing requests by multiple microcontrollers for a shared memory. One of the microcontrollers is designated to have a higher priority than the other microcontroller(s). In the case of competing requests, while one microcontroller is granted access to the memory, the other microcontroller performs other processing, and polls a memory status register to determine when the memory is available. Since the waiting processor performs other operations, as opposed to idling, the efficiency of the microcontroller is improved.