Abstract: A clock signal generator that generates a second clock signal and clock information from a transfer first clock signal and based on a thinning rate, the number of horizontal pre-blank data pieces, the number of effective horizontal pixels, and the number of horizontal post-blank data pieces stored in a register. A thinning processor retrieves image data in accordance with the first clock signal and a horizontal synchronization signal. The thinning processor performs a thinning process on the image data to generate thinned image data and stores the thinned image data in a memory. A read controller sequentially reads the thinned image data from the memory in accordance with the second clock signal having a frequency lower than the first clock signal.

Abstract: A clock signal generator that generates a second clock signal and clock information from a transfer first clock signal and based on a thinning rate, the number of horizontal pre-blank data pieces, the number of effective horizontal pixels, and the number of horizontal post-blank data pieces stored in a register. A thinning processor retrieves image data in accordance with the first clock signal and a horizontal synchronization signal. The thinning processor performs a thinning process on the image data to generate thinned image data and stores the thinned image data in a memory. A read controller sequentially reads the thinned image data from the memory in accordance with the second clock signal having a frequency lower than the first clock signal.