Patents by Inventor Kunihiro Tsubosaki

Kunihiro Tsubosaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6589818
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406). The semiconductor chip (105′) is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105′) is hot-pressed by means of a heating head (106) for bonding on the substrate (102). In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: July 8, 2003
    Assignee: Hitachi. Ltd.
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Publication number: 20030124770
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Application
    Filed: February 24, 2003
    Publication date: July 3, 2003
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Patent number: 6573158
    Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: June 3, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
  • Patent number: 6558980
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: May 6, 2003
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Patent number: 6531760
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: March 11, 2003
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6521981
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: February 18, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20030027376
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).
    Type: Application
    Filed: October 1, 2002
    Publication date: February 6, 2003
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6514796
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406). The semiconductor chip (105′) is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105′) is hot-pressed by means of a heating head (106) for bonding on the substrate (102). In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: February 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6515371
    Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 4, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Akita Electronics Co., Ltd.
    Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
  • Publication number: 20030001286
    Abstract: A semiconductor chip and an organic substrate are bonded together in an atmosphere having a reduced moisture content through Au bumps which have been subjected to a cleaning treatment therebetween. Using this bonding technique, a semiconductor chip and an organic substrate can be bonded together in a sufficiently high strength with use of Au bumps having a diameter of not larger than 300 &mgr;m, a height of not smaller than 50 &mgr;m, and a height/diameter ratio of not lower than 1/5, thus indicating a reduced strain.
    Type: Application
    Filed: September 4, 2002
    Publication date: January 2, 2003
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Asao Nishimura, Kunihiro Tsubosaki
  • Publication number: 20020192871
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≧1.2 t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.
    Type: Application
    Filed: July 26, 2002
    Publication date: December 19, 2002
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Publication number: 20020180010
    Abstract: A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is less in thickness than the tape base material 1a, while sealing by a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, let the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a be identical to a stress neutral plane of the TCP as a whole.
    Type: Application
    Filed: July 20, 1999
    Publication date: December 5, 2002
    Inventors: KUNIHIRO TSUBOSAKI, TOSHIO MIYAMOTO
  • Publication number: 20020175409
    Abstract: The semiconductor device comprises an insulation layer formed on surfaces of semiconductor chips where the electrodes are formed, and a wiring layer formed on the insulation layer. The wiring layer formed on the insulation layer and the electrodes of the semiconductor chips are electrically connected to each other via connection members, such as wire bumps, etc. formed on the electrodes of the semiconductor chip.
    Type: Application
    Filed: July 31, 2001
    Publication date: November 28, 2002
    Inventor: Kunihiro Tsubosaki
  • Publication number: 20020160185
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Application
    Filed: May 6, 2002
    Publication date: October 31, 2002
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6472727
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: October 29, 2002
    Assignees: Hitachi, Ltd., Hitahi Microcomputer System, Ltd, Hitachi ULSI Engineering Corp.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20020153596
    Abstract: In a lead frame used for forming semiconductor package, a roughened plating layer 10 with excessive uneven surface is formed at least on the surface of lead frame brought into contact with molding compound 7 and metallic plating is made on areas of the rough surface 10 needed for wire bonding to form plating portions for connection. The surface of lead frame at least brought into contact with molding compound is covered with roughened plating layer 10 with excessive uneven surface so that the adhesion of molding compound to the lead frame is excellent due to the function of the roughened plating layer anchoring molding compound 7 to the lead frame. Therefore, the package crack and the cut of wires do not occur.
    Type: Application
    Filed: March 18, 2002
    Publication date: October 24, 2002
    Inventors: Kunihiro Tsubosaki, Chikao Ikenaga, Kenji Matsumura
  • Publication number: 20020137261
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads. In a molding member-sealed semiconductor device wherein the semiconductor chip is fixed to the heat radiation plate, the tip thickness t′ of the inner leads is made less than the thickness t of the other portions of the inner leads secured to the heat radiation plate.
    Type: Application
    Filed: May 23, 2002
    Publication date: September 26, 2002
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Publication number: 20020137262
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.
    Type: Application
    Filed: May 23, 2002
    Publication date: September 26, 2002
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Patent number: 6445076
    Abstract: An insulating adhesive for electronic parts, which is to be used for bonding a semiconductor chip to a lead frame and comprises a resin and a solvent, the resin having (A) a weight average molecular weight (Mw) of 30,000 to 300,000 based on conversion into polystyrene and (B) a ratio of weight average molecular weight (Mw)/number average molecular weight (Mn) of 5 or less, and (C) the insulating adhesive for electronic parts having a viscosity of 5,000 to 100,000 mPa.s at a rotation number of 10 rpm and a viscosity ratio (&eegr;1 rpm/&eegr;10 rpm) of 1.0 to 6.0 as measured at 25° C. with an E-type viscometer.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 3, 2002
    Assignees: Hitachi Chemical Company, Ltd., Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takehiro Shimizu, Takafumi Dohdoh, Kazumi Tameshige, Hidekazu Matsuura, Yoshihiro Nomura, Kunihiro Tsubosaki, Toshihiro Shiotsuki, Kazunari Suzuki, Tomoko Higashino
  • Patent number: 6441502
    Abstract: A member for mounting of semiconductor is comprised of a substrate, a concave portions for electrode and a concave portion for wire formed on one surface of the substrate, electrode terminals formed in the concave portions for electrode, and a wire formed in the concave portion for wire, in which the concave portions for electrode terminals are formed deeper than the concave portions for wire. In the pattern-forming process, resist pattern having an opening for wire and openings for electrode in which a width of the openings for electrode is larger than a width of the portion for wire is formed on one surface of a substrate. In the etching process, a substrate is half-cut by etching a substrate through the resist pattern as a mask so that concave portions for electrode and a opening for wire are formed on the surface of the substrate.
    Type: Grant
    Filed: December 23, 2000
    Date of Patent: August 27, 2002
    Assignee: Dainippon Printing Co., Ltd.
    Inventors: Junichi Yamada, Hideki Sato, Kunihiro Tsubosaki, Yo Shimazaki