Patents by Inventor Kunihito Ohshima

Kunihito Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device for reducing forward voltage by using OHMIC contact
    Patent number: 7573096
    Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: August 11, 2009
    Assignee: Shindengen Electric Manufacturing Co, Ltd.
    Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Ohshima, Masato Itoi
  • Semiconductor Device
    Publication number: 20080135925
    Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.
    Type: Application
    Filed: February 16, 2005
    Publication date: June 12, 2008
    Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Ohshima, Masato Itoi
  • Two-terminal semiconductor overcurrent limiter
    Patent number: 6469352
    Abstract: A semiconductor overcurrent limiter having input and output terminals includes a depletion type vertical MOSFET, a depletion type lateral MOSFET, and a zener diode. A back gate of the lateral MOSFET is formed in common with a drain electrode of the vertical MOSFET to provide the input terminal, and a gate of the vertical MOSFET is connected to an anode of the zener diode to provide the output terminal. Further, a source electrode of the vertical MOSFET is connected to source and gate electrodes of the lateral MOSFET and a cathode electrode of the zener diode.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: October 22, 2002
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Kunihito Ohshima, Masaya Shirota, Toshikazu Tezuka
  • Two-terminal semiconductor overcurrent limiter
    Publication number: 20020000568
    Abstract: A semiconductor overcurrent limiter having input and output terminals includes a depletion type vertical MOSFET, a depletion type lateral MOSFET, and a zener diode. A back gate of the lateral MOSFET is formed in common with a drain electrode of the vertical MOSFET to provide the input terminal, and a gate of the vertical MOSFET is connected to an anode of the zener diode to provide the output terminal. Further, a source electrode of the vertical MOSFET is connected to source and gate electrodes of the lateral MOSFET and a cathode electrode of the zener diode.
    Type: Application
    Filed: June 20, 2001
    Publication date: January 3, 2002
    Inventors: Kunihito Ohshima, Masaya Shirota, Toshikazu Tezuka