Patents by Inventor Kuniki Morita

Kuniki Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120246408
    Abstract: A physical process ID (PPID) is stored for each cache block of each set, and a MAX WAY number for each PPID value is stored for each of index values #1 to #n. A MAX WAY number corresponding to a certain PPID value in a certain index value indicates the maximum number of cache blocks having the PPID value, which can be stored in the index value. The number of ways at the time of a cache miss is controlled not to exceed the MAX WAY number of each PPID value for each index value.
    Type: Application
    Filed: January 27, 2012
    Publication date: September 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shuji YAMAMURA, Kuniki Morita
  • Patent number: 8060698
    Abstract: A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 15, 2011
    Assignee: Fujitsu Limited
    Inventors: Souta Kusachi, Kuniki Morita, Masaki Ukai, Tomoyuki Okawa
  • Patent number: 8006139
    Abstract: A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Okawa, Kuniki Morita
  • Patent number: 7765387
    Abstract: A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: July 27, 2010
    Assignee: Fujitsu Limited
    Inventors: Ryuichi Sunayama, Kuniki Morita, Aiichiro Inoue
  • Publication number: 20080320327
    Abstract: A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.
    Type: Application
    Filed: August 26, 2008
    Publication date: December 25, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki OKAWA, Kuniki MORITA
  • Publication number: 20080282037
    Abstract: A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.
    Type: Application
    Filed: July 15, 2008
    Publication date: November 13, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Souta Kusachi, Kuniki Morita, Masaki Ukai, Tomoyuki Okawa
  • Publication number: 20040003207
    Abstract: A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.
    Type: Application
    Filed: January 28, 2003
    Publication date: January 1, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Ryuichi Sunayama, Kuniki Morita, Aiichiro Inoue
  • Patent number: 4953835
    Abstract: Wire of an oval type cross sectional shape having a surface formed of a semicircle and semiellipse tangent to each other has been used for coiled springs. Stress distribution in wire of such a shape can be improved by increasing the dimension of the spring wire in a direction perpendicular to the axis of the spring. One such cross sectional shape is formed by semicircle and semiellipse portions connected by straight lines.
    Type: Grant
    Filed: July 12, 1989
    Date of Patent: September 4, 1990
    Assignee: Murata Hatsujo Co. Ltd.
    Inventors: Yukio Matsumoto, Horiyuki Saito, Kuniki Morita
  • Patent number: 4735403
    Abstract: It is known that a sectional shape of a spring wire can be formed into an oval made by a semicircle and a semiellipse. However, it has been found that such a shape is not the best obtainable, and that stress distribution can be improved by increasing the diameter of the spring wire slightly in a portion where the stress is greatest, along the semielliptical surface. Parameters are disclosed for determining dimensions that result in increased energy efficiency.
    Type: Grant
    Filed: January 28, 1987
    Date of Patent: April 5, 1988
    Assignee: Murata Hatsujo Co., Ltd.
    Inventors: Yukio Matsumoto, Noriyuki Saito, Kuniki Morita