Patents by Inventor Kuniko Ishikawa
Kuniko Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8861903Abstract: A method of manufacturing an optical waveguide device, the method includes: inserting an inclined surface of a mold which is inclined relative to a surface of a substrate including an optical waveguide member into a through hole in which the optical waveguide member is exposed from one surface side of the substrate; locating an optical component above an opening of the through hole on the other surface side of the substrate; injecting an underfill material into between the optical component and the other surface and into the through hole; and curing the underfill material to form a mirror surface.Type: GrantFiled: December 11, 2012Date of Patent: October 14, 2014Assignee: Fujitsu LimitedInventors: Takatoyo Yamakami, Takashi Kubota, Kuniko Ishikawa, Hidehiko Kira
-
Publication number: 20140103117Abstract: There is provided an RFID tag, which includes: a first substrate having flexibility and configured to include an antenna provided on a first surface of the first substrate; a second substrate; an IC chip mounted on a first surface of the second substrate; an anisotropic conductive rubber configured to contact the first substrate to the second substrate with the IC chip facing the first surface of the first substrate and to contact a terminal of the IC chip to the antenna; and an exterior rubber configured to cover the first substrate, the second substrate, and the IC chip.Type: ApplicationFiled: August 19, 2013Publication date: April 17, 2014Applicant: FUJITSU LIMITEDInventors: Shuichi TAKEUCHI, Norio KAINUMA, Kuniko ISHIKAWA, Tetsuya TAKAHASHI, Kenji KOBAE
-
Publication number: 20130313309Abstract: A conductive bonding material includes: a solder component including a metal foamed body of a first metal having at least one pore, the pore absorbs melted first metal when the metal foamed body is heated at a temperature higher than the melting point of the first metal, and a second metal having a melting point lower than the melting point of the first metal.Type: ApplicationFiled: March 28, 2013Publication date: November 28, 2013Inventors: Masayuki KITAJIMA, Takatoyo YAMAKAMI, Takashi KUBOTA, Kuniko ISHIKAWA
-
Publication number: 20130259421Abstract: A method of manufacturing an optical waveguide device, the method includes: inserting an inclined surface of a mold which is inclined relative to a surface of a substrate including an optical waveguide member into a through hole in which the optical waveguide member is exposed from one surface side of the substrate; locating an optical component above an opening of the through hole on the other surface side of the substrate; injecting an underfill material into between the optical component and the other surface and into the through hole; and curing the underfill material to form a mirror surface.Type: ApplicationFiled: December 11, 2012Publication date: October 3, 2013Applicant: FUJITSU LIMITEDInventors: Takatoyo YAMAKAMI, Takashi KUBOTA, Kuniko ISHIKAWA, Hidehiko KIRA
-
Publication number: 20130249087Abstract: An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads.Type: ApplicationFiled: April 22, 2013Publication date: September 26, 2013Applicant: FUJITSU LIMITEDInventors: Kimio Nakamura, Takayoshi Matsumura, Yoshiyuki Satoh, Kuniko Ishikawa, Kenji Kobae
-
Patent number: 8418910Abstract: An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.Type: GrantFiled: February 7, 2012Date of Patent: April 16, 2013Assignee: Fujitsu LimitedInventors: Takatoyo Yamakami, Takashi Kubota, Kuniko Ishikawa, Masayuki Kitajima
-
Publication number: 20130087605Abstract: A conductive bonding material comprising: a first metal particle; a second metal particle having an average particle diameter larger than an average particle diameter of the first metal particle; and a third metal particle having an average particle diameter larger than the average particle diameter of the first metal particle, a relative density larger than a relative density of the first metal particle, and a melting point higher than a melting point of the second metal particle.Type: ApplicationFiled: August 28, 2012Publication date: April 11, 2013Applicant: FUJITSU LIMITEDInventors: Takashi KUBOTA, Masayuki KITAJIMA, Takatoyo YAMAKAMI, Kuniko ISHIKAWA
-
Publication number: 20120248616Abstract: To provide an electronic component, containing: a wiring board containing electrode pads; a component including a plurality of electrodes, the component being mounted on the wiring board; a sealing resin covering the component; and a plurality of terminals configured to connect a wiring provided within the wiring board to an external substrate, wherein the plurality of electrodes and the electrode pads are connected with solder, and wherein a first resin layer and a second resin layer are provided between the solder and the sealing resin in this order from the side of the solder, where the first resin layer has a first Young's modulus and the second resin layer has a second Young's modulus larger than the first Young's modulus.Type: ApplicationFiled: January 30, 2012Publication date: October 4, 2012Applicant: FUJITSU LIMITEDInventors: Masayuki KITAJIMA, Takatoyo Yamakami, Takashi Kubota, Kuniko Ishikawa
-
Publication number: 20120211549Abstract: An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.Type: ApplicationFiled: February 7, 2012Publication date: August 23, 2012Applicant: FUJITSU LIMITEDInventors: Takatoyo YAMAKAMI, Takashi KUBOTA, Kuniko ISHIKAWA, Masayuki KITAJIMA
-
Patent number: 8076233Abstract: A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating roller has passed over the solder sheet.Type: GrantFiled: September 17, 2009Date of Patent: December 13, 2011Assignee: Fujitsu LimitedInventors: Kuniko Ishikawa, Norio Kainuma, Kenji Kobae
-
Publication number: 20110079896Abstract: A semiconductor device fabrication method, comprising the steps of: forming a solder portion on an electrode of a substrate on which a semiconductor chip is to be mounted; applying a resin layer onto the substrate to a thickness such that a top region of the solder portion is exposed; curing the resin layer; providing a thermosetting underfill material over a region where the semiconductor chip is to be mounted; placing an electrode of the semiconductor chip face down on the solder portion in such a manner that the electrode faces the solder portion; and heating the underfill material and the solder portion.Type: ApplicationFiled: September 28, 2010Publication date: April 7, 2011Applicant: FUJITSU LIMITEDInventors: Yoshiyuki SATOH, Kenji KOBAE, Kimio NAKAMURA, Takayoshi MATSUMURA, Kuniko ISHIKAWA
-
Publication number: 20100327435Abstract: An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads.Type: ApplicationFiled: June 24, 2010Publication date: December 30, 2010Applicant: FUJITSU LIMITEDInventors: Kimio Nakamura, Takayoshi Matsumura, Yoshiyuki Satoh, Kuniko Ishikawa, Kenji Kobae
-
Patent number: 7833831Abstract: An electronic component is equipped with electrode protrusions that make it possible to mount the electronic component without covering connection pads of a circuit board with solder and to dispose the connection pads of the circuit board with a narrow pitch while preventing electrical shorting of the connection electrodes during mounting. A method of manufacturing an electronic component equipped with connection electrodes, where electrode protrusions are covered with solder, includes a step of heating a solder sheet to a semi-molten state and pressing the electronic component onto the solder sheet to place the electrode protrusions in contact with the solder sheet and a step of retracting the electronic component from a position where the electrode protrusions contact the solder sheet to transfer solder onto outside surfaces of the electrode protrusions that contacted the solder sheet.Type: GrantFiled: December 6, 2007Date of Patent: November 16, 2010Assignee: Fujitsu LimitedInventors: Norio Kainuma, Kuniko Ishikawa, Hidehiko Kira
-
Patent number: 7828193Abstract: In a method of mounting an electronic component on a substrate, electrode terminals on at least one of the substrate and the electronic component are composed of solder bumps. The electrode terminals of the substrate and the electrode terminals of the electronic component are placed in contact and ultrasonic vibration is applied to at least one of the substrate and the electronic component to provisionally bond the electrode terminals together. A gap between the substrate and the electronic component is then filled with flux fill, and the electrode terminals of the substrate and the electronic component are bonded by reflowing the solder bumps.Type: GrantFiled: December 14, 2007Date of Patent: November 9, 2010Assignee: Fujitsu LimitedInventors: Kuniko Ishikawa, Norio Kainuma, Hidehiko Kira
-
Publication number: 20100075493Abstract: A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating roller has passed over the solder sheet.Type: ApplicationFiled: September 17, 2009Publication date: March 25, 2010Applicant: FUJITSU LIMITEDInventors: Kuniko Ishikawa, Norio Kainuma, Kenji Kobae
-
Patent number: 7566586Abstract: A method of manufacturing a semiconductor device flip-chip bonds electrode terminals of a substrate and a semiconductor chip together by solid-phase diffusion and underfills a gap between the substrate and the semiconductor chip with a thermosetting resin without the bonds between the terminals breaking due to heat in an underfill hardening step. The method includes a bonding step of flip-chip bonding the electrode terminals of the substrate and the semiconductor chip by solid-phase diffusion, an underfill filling step of filling the gap between the substrate and the semiconductor chip with the underfill material, and the underfill hardening step where the underfill material is heated to the hardening temperature to harden the underfill material. During the underfill hardening step, a member with a lower coefficient of thermal expansion out of the substrate and the semiconductor chip is heated to a higher temperature than the other member.Type: GrantFiled: December 6, 2006Date of Patent: July 28, 2009Assignee: Fujitsu LimitedInventors: Norio Kainuma, Hidehiko Kira, Kenji Kobae, Kimio Nakamura, Kuniko Ishikawa, Yukio Ozaki
-
Publication number: 20080203138Abstract: In a method of mounting an electronic component on a substrate, electrode terminals on at least one of the substrate and the electronic component are composed of solder bumps. The electrode terminals of the substrate and the electrode terminals of the electronic component are placed in contact and ultrasonic vibration is applied to at least one of the substrate and the electronic component to provisionally bond the electrode terminals together. A gap between the substrate and the electronic component is then filled with flux fill, and the electrode terminals of the substrate and the electronic component are bonded by reflowing the solder bumps.Type: ApplicationFiled: December 14, 2007Publication date: August 28, 2008Applicant: FUJITSU LIMITEDInventors: Kuniko Ishikawa, Norio Kainuma, Hidehiko Kira
-
Publication number: 20080206587Abstract: An electronic component is equipped with electrode protrusions that make it possible to mount the electronic component without covering connection pads of a circuit board with solder and to dispose the connection pads of the circuit board with a narrow pitch while preventing electrical shorting of the connection electrodes during mounting. A method of manufacturing an electronic component equipped with connection electrodes, where electrode protrusions are covered with solder, includes a step of heating a solder sheet to a semi-molten state and pressing the electronic component onto the solder sheet to place the electrode protrusions in contact with the solder sheet and a step of retracting the electronic component from a position where the electrode protrusions contact the solder sheet to transfer solder onto outside surfaces of the electrode protrusions that contacted the solder sheet.Type: ApplicationFiled: December 6, 2007Publication date: August 28, 2008Applicant: FUJITSU LIMITEDInventors: Norio Kainuma, Kuniko Ishikawa, Hidehiko Kira
-
Publication number: 20070264752Abstract: A method of manufacturing a semiconductor device flip-chip bonds electrode terminals of a substrate and a semiconductor chip together by solid-phase diffusion and underfills a gap between the substrate and the semiconductor chip with a thermosetting resin without the bonds between the terminals breaking due to heat in an underfill hardening step. The method includes a bonding step of flip-chip bonding the electrode terminals of the substrate and the semiconductor chip by solid-phase diffusion, an underfill filling step of filling the gap between the substrate and the semiconductor chip with the underfill material, and the underfill hardening step where the underfill material is heated to the hardening temperature to harden the underfill material. During the underfill hardening step, a member with a lower coefficient of thermal expansion out of the substrate and the semiconductor chip is heated to a higher temperature than the other member.Type: ApplicationFiled: December 6, 2006Publication date: November 15, 2007Applicant: FUJITSU LIMITEDInventors: Norio Kainuma, Hidehiko Kira, Kenji Kobae, Kimio Nakamura, Kuniko Ishikawa, Yukio Ozaki