Abstract: A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

Abstract: A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

Abstract: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Abstract: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Abstract: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Abstract: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Abstract: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Abstract: A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.

Abstract: An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the present invention, a semiconductor device comprises a semiconductor substrate of a first conductivity type, a digital circuit part and an analog circuit part provided on the semiconductor substrate, a plurality of wells of the first conductivity type formed in either the analog circuit part or the digital circuit part, and a first deep well of a second conductivity type, which is the opposite conductivity type to the first conductivity type, isolating some of the plurality of wells from the semiconductor substrate.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a lower interconnection on a semiconductor substrate; forming a first interlayer insulation film in which the lower interconnection is buried; forming an MIM capacitive element on the first interlayer insulation film, the MIM capacitive element being formed by layering a lower electrode, a dielectric film, and an upper electrode; forming a second interlayer insulation film in which the MIM capacitive element is buried; forming via holes in the second interlayer insulation film so as to reach the lower electrode; forming a connection plug by filling the via hole with conductive film; and forming an upper interconnection to be connected to the connection plug above the second interlayer insulation film.

Abstract: A technique for reducing influences of the bias magnetic field developed by yokes used for concentrating the magnetic field on magnetoresistance elements, on MRAM operations. An MRAM is composed of a plurality of magnetoresistance elements having magnetic anisotropy in a first direction; a wiring extended in a second direction different from the first direction, through which a write current flows for writing data into the magnetoresistance elements; and a yoke layer formed of ferromagnetic material, extended along the second direction, and covering at least a portion of a surface of the wiring. The plurality of magnetoresistance elements include a first magnetoresistance element, and a second magnetoresistance element of which the distance from an end of the yoke layer is further than that of the first magnetoresistance element. The first magnetoresistance element has a magnetic anisotropy stronger than that of the second magnetoresistance element.

Abstract: On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.

Abstract: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased.

Abstract: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased.

Abstract: As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure comprises a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also comprises a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition.

Abstract: A magnetic memory includes a substrate, a lower portion structure of a magnetic element, an upper portion structure of the magnetic element, and a sidewall insulating film. The lower portion structure of the magnetic element is a portion of the magnetic element provided on the upside of the substrate. The upper portion structure of the magnetic element is a remaining portion of the magnetic element provided on the upside of the lower portion structure of the magnetic element. The sidewall insulating film is provided to surround the upper portion structure of the magnetic element and is formed of an insulating material. That is, the lower portion structure of the magnetic element is formed from one layer or a plurality of layers on a side close to the substrate, among a plurality of laminated films of the magnetic element provided on the upside of the substrate.

Abstract: A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.

Abstract: An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the present invention, a semiconductor device comprises a semiconductor substrate of a first conductivity type, a digital circuit part and an analog circuit part provided on the semiconductor substrate, a plurality of wells of the first conductivity type formed in either the analog circuit part or the digital circuit part, and a first deep well of a second conductivity type, which is the opposite conductivity type to the first conductivity type, isolating some of the plurality of wells from the semiconductor substrate.