Patents by Inventor Kuniko Miyakawa
Kuniko Miyakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6114765Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in, the form of a substitutional solid solution.Type: GrantFiled: December 17, 1998Date of Patent: September 5, 2000Assignee: NEC CorporationInventors: Kunihiro Fujii, Ken Inoue, Kuniko Miyakawa, Kaoru Mikagi
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Patent number: 6069045Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not more than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not more than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in the form of a substitutional solid solution.Type: GrantFiled: December 17, 1998Date of Patent: May 30, 2000Assignee: NEC CorporationInventors: Kunihiro Fujii, Ken Inoue, Kuniko Miyakawa, Kaoru Mikagi
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Patent number: 5990005Abstract: A method of burying a conductive metal into a contact hole formed in an insulation film formed over a silicon substrate. Within the contact hole a refractory metal silicide layer has been formed on the silicon substrate and a barrier metal layer has been formed on the refractory metal silicide layer and further a conductive metal film has been formed on the barrier metal layer.Type: GrantFiled: February 10, 1997Date of Patent: November 23, 1999Assignee: NEC CorporationInventors: Kazuyuki Hirose, Kuniko Miyakawa
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Patent number: 5880505Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not less than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in the form of a substitutional solid solution.Type: GrantFiled: June 2, 1997Date of Patent: March 9, 1999Assignee: NEC CorporationInventors: Kunihiro Fujii, Ken Inoue, Kuniko Miyakawa, Kaoru Mikagi
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Patent number: 5869397Abstract: On a silicon substrate (1) is formed a MOS transistor which comprises a gate oxide film (3), a polysilicon gate electrode (4), an LDD diffusion layer (5) and a source/drain diffusion layer (7). A Ti film (8) is formed over the entire surface of the MOS transistor, the surface areas of the source/drain diffusion layer (7) and the polysilicon gate electrode (4) are silicified to form Ti silicide film (9, 10). Thereafter, W or Ta is ion-implanted as an alloy forming material into Ti silicide (10), and an anneal treatment is performed to react doped W or Ta with Ti silicide (10) and form TiW.sub.x Si.sub.y or TiTa.sub.x Si.sub.y (11).Type: GrantFiled: January 13, 1998Date of Patent: February 9, 1999Assignee: NEC CorporationInventor: Kuniko Miyakawa
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Patent number: 5851915Abstract: In a method of manufacturing a semiconductor device including a first and a second insulator film and a first and a second conductive layer held to the first and said second insulator films, respectively. The first insulator film is formed to have a first wiring trench along an upper surface of the first insulator film and a first through hole extending from the first wiring trench to a lower surface of the first insulator film. A first conductive material is deposited on the upper surface of the first insulator film to fill the first wiring trench and the first through hole. Thereafter, the first conductive material is partially removed to have an upper surface coplanar with the upper surface of the first insulator film. As a result, the first conductive material becomes the first wiring layer. Next, the second insulator film and the second wiring layer are formed in the manner which is similar to that of forming the first insulator film and the first wiring layer.Type: GrantFiled: June 9, 1997Date of Patent: December 22, 1998Assignee: NEC CorporationInventor: Kuniko Miyakawa
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Patent number: 5686760Abstract: In a semiconductor device having a wiring groove in alignment with a contact hole, a wiring structure includes a diffusion preventing film formed on the bottom and side walls of the wiring groove, the diffusion preventing film being composed of a barrier metal for preventing diffusion of Cu and an element which cooperates with Cu so as to form a eutectic Cu-alloy having a eutectic temperature of not higher than 850.degree. C. A Cu film is formed on the diffusion preventing film so as to fill up the wiring groove, so that Cu and the above mentioned element actually form the eutectic Cu-alloy having the eutectic temperature of not higher than 850.degree. C.Type: GrantFiled: November 16, 1995Date of Patent: November 11, 1997Assignee: NEC CorporationInventor: Kuniko Miyakawa
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Patent number: 5543357Abstract: The present invention discloses a process for manufacturing a semiconductor device in which characteristics of an aluminum alloy film are prevented from deteriorating, when a titanium film is used as an under film and the aluminum alloy film is heated to fill a via hole therewith. Interlayered insulating film is formed on a first aluminum wire, and after the formation of a via hole which reaches the first aluminum wire, a titanium film and an aluminum alloy film are formed in turn by a sputtering process. Next, a silicon substrate is heated up to 450.degree. to 500.degree. C. to melt the aluminum alloy film, thereby filling the via hole therewith. In this case, the thickness of the titanium film is set to 10% or less of the thickness of the aluminum alloy film and at most 25 nm.Type: GrantFiled: December 8, 1994Date of Patent: August 6, 1996Assignee: NEC CorporationInventors: Yoshiaki Yamada, Nobukazu Ito, Kuniko Miyakawa, Michiko Yamanaka
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Patent number: 5278449Abstract: In this semiconductor device, contact holes extending from a lower interconnection layer containing diffusion layers at the surface of a Si substrate to an Al-involved interconnection layer formed above the Sis substrate through the intermediation of an interlayer dielectric film are filled with Al alloy having a eutectic point lower than that of Al-Si alloy. Then, for example, an Al-Ge alloy is sputtered, reflowed and allowed to react with the Si film to convert into an Al-Ge-Si alloy. At the stage of forming the Al-Ge-Si alloy, the reflow ceases. This brings the reduction of junction leakage current from the diffusion layers. Similarly in the case of a high aspect ratio of contact hole, this technique enables the contact hole to be fully filled with the above-mentioned Al alloy.Type: GrantFiled: August 31, 1992Date of Patent: January 11, 1994Assignee: Nec CorporationInventor: Kuniko Miyakawa
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Patent number: 5169803Abstract: In this semiconductor device, contact holes extending from a lower interconnection layer containing diffusion layers at the surface of a Si substrate to an Al-involved interconnection layer formed above the Si substrate through the intermediation of an interlayer dielectric film are filled with Al alloy having an eutectic point lower than that of Al-Si alloy. Then, for example, an Al-Ge alloy is sputtered, reflowed and allowed to react with the Si film to convert into an Al-Ge-Si alloy. At the stage of forming the Al-Ge-Si alloy, the reflow ceases. This brings the reduction of junction leakage current from the diffusion layers. Similarly in the case of a high aspect ratio of contact hole, this technique enables to fully fill the contact hole with the above-mentioned Al alloy.Type: GrantFiled: November 27, 1991Date of Patent: December 8, 1992Assignee: NEC CorporationInventor: Kuniko Miyakawa