Abstract: Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.

Abstract: Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.

Abstract: A data transmission system which provides a better level of transmission quality, without being affected by skew variations. A serial-to-parallel converter reforms a serial data stream into a set of parallel data streams. A sync pattern inserter generates and inserts sync patterns to the parallel data streams. The resultant sync pattern-inclusive data streams are, however, distorted with some propagation delay skews when they arrive at the receiving end. A data retimer extracts a reference clock from one of the received data streams, and retimes all streams with that reference clock, thus producing a set of retimed data streams. An in-sync detector produces pulse signals indicating the presence of sync patterns in the retimed data streams and determines whether each of those streams is in in-sync state. A phase adjuster identifies the propagation delay skews by examining the pulse signals, and adjusts the phase of each data stream to eliminate them.

Abstract: A data transmission system which provides a better level of transmission quality, without being affected by skew variations. A serial-to-parallel converter reforms a serial data stream into a set of parallel data streams. A sync pattern inserter generates and inserts sync patterns to the parallel data streams. The resultant sync pattern-inclusive data streams are, however, distorted with some propagation delay skews when they arrive at the receiving end. A data retimer extracts a reference clock from one of the received data streams, and retimes all streams with that reference clock, thus producing a set of retimed data streams. An in-sync detector produces pulse signals indicating the presence of sync patterns in the retimed data streams and determines whether each of those streams is in in-sync state. A phase adjuster identifies the propagation delay skews by examining the pulse signals, and adjusts the phase of each data stream to eliminate them.