Patents by Inventor Kuninori ISHII

Kuninori ISHII has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10489131
    Abstract: Upon reception of a first compilation command that contains an instruction for executing link time optimization, the apparatus generates a first object file that contains source-code information including a source code and does not contain an object code. Upon reception of a first link command that contains the instruction for executing the link time optimization, the apparatus generates the object code by executing the link time optimization and compilation on the source code information contained in the first object file, and generates a second object file that contains the generated object code. Upon reception of a second link command that does not contain an instruction for executing the link time optimization, the apparatus generates the object code by executing the compilation on the source code information contained in the first object file, and generates a third object file that contains the generated object code.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: November 26, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kuninori Ishii, Naoki Sueyasu
  • Patent number: 10481883
    Abstract: An information processor including a memory; and a processor coupled to the memory and method thereof. The processor is configured to store first identification information of a first source file corresponding to an object file that is not linked, judge whether second identification information of a second source file specified as a target of compilation is stored in the memory, and generate an object file through compilation on a third source file where the second identification information of the second source file is stored in the memory. The processor is also configured to perform inter-file optimization on the second source file and the third source file to generate a plurality of intermediate files and generate a plurality of object files through compilation on the plurality of generated intermediate files.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kuninori Ishii, Toshihiro Suzuki, Naoki Sueyasu
  • Patent number: 10089088
    Abstract: A computer configured to perform compiling, including a memory configured to store a source program and a processor, the processor is configured to execute a method which includes; compiling the source program, wherein a number of cycles desired for executing each function included in the source program and information indicating a call relationship between a task and a function called by the task are generated, and performing link processing, wherein a number of cycles desired for executing each task based on the number of cycles desired for executing each function and the call relationship.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: October 2, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Kuninori Ishii
  • Publication number: 20180210718
    Abstract: Upon reception of a first compilation command that contains an instruction for executing link time optimization, the apparatus generates a first object file that contains source-code information including a source code and does not contain an object code. Upon reception of a first link command that contains the instruction for executing the link time optimization, the apparatus generates the object code by executing the link time optimization and compilation on the source code information contained in the first object file, and generates a second object file that contains the generated object code. Upon reception of a second link command that does not contain an instruction for executing the link time optimization, the apparatus generates the object code by executing the compilation on the source code information contained in the first object file, and generates a third object file that contains the generated object code.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 26, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Kuninori ISHII, Naoki Sueyasu
  • Publication number: 20180052668
    Abstract: An information processor includes: a memory; and a processor coupled to the memory and the processor configured to: store first identification information of a first source file corresponding to an object file that is not linked; judge whether second identification information of a second source file specified as a target of compilation is stored in the memory, and generate an object file through compilation on a third source file other than the second source file where the second identification information of the second source file is stored in the memory; perform inter-file optimization on the second source file and the third source file other than the second source file to generate a plurality of intermediate files; and generate a plurality of object files through compilation on the plurality of generated intermediate files.
    Type: Application
    Filed: July 31, 2017
    Publication date: February 22, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Kuninori ISHII, TOSHIHIRO SUZUKI, Naoki Sueyasu
  • Publication number: 20160371068
    Abstract: A computer configured to perform compiling, including a memory configured to store a source program and a processor, the processor is configured to execute a method which includes; compiling the source program, wherein a number of cycles desired for executing each function included in the source program and information indicating a call relationship between a task and a function called by the task are generated, and performing link processing, wherein a number of cycles desired for executing each task based on the number of cycles desired for executing each function and the call relationship.
    Type: Application
    Filed: May 26, 2016
    Publication date: December 22, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Kuninori ISHII
  • Patent number: 9430203
    Abstract: A storage unit stores source code including loop processing that is written with an array referenced by an index, a loop variable, and a parameter. A computing unit generates a conditional expression indicating that the index of the array satisfies a predetermined condition, using the loop variable and the parameter. The computing unit generates determination information on the parameter, by eliminating the loop variable from the conditional expression through formula manipulation. Then, the computing unit generates object code corresponding to the source code in accordance with the determination information.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: August 30, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kuninori Ishii, Masanori Yamanaka, Masaki Arai
  • Publication number: 20150135171
    Abstract: A storage unit stores source code including loop processing that is written with an array referenced by an index, a loop variable, and a parameter. A computing unit generates a conditional expression indicating that the index of the array satisfies a predetermined condition, using the loop variable and the parameter. The computing unit generates determination information on the parameter, by eliminating the loop variable from the conditional expression through formula manipulation. Then, the computing unit generates object code corresponding to the source code in accordance with the determination information.
    Type: Application
    Filed: October 24, 2014
    Publication date: May 14, 2015
    Inventors: Kuninori ISHII, Masanori YAMANAKA, MASAKI ARAI