Abstract: A digital automatic gain control circuit provided with a first AGC loop and a second AGC loop; activated alternately. The first AGC loop is activated when an input signal is initially supplied. The loop produces a certain digital value calculated as an inverse number of the digital level of the input through predetermined digital arithmetic operations utilizing an approximation polynominal. The calculated digital value is then preset in certain portions of the second AGC loop. The second AGC loop starts operating by using said present value, then uses the digital level of the input itself, instead of the preset value, and produces an automatic gain controlled digital output. Utilizing said preset value as an initial input to the second AGC loop allows for rapid stabilization of the automatic gain controlled digital output.

Abstract: The present invention relates to a digital phase locked loop circuit, particularly to a circuit which realizes accurately digital phase locked loop pull-in operation at a high speed with a simplified circuit structure.In the present invention, in order to obtain a phase difference between a single frequency signal and the digital phase locked loop clock signal which is obtained by dividing a specified frequency signal with a dividing counter, the phase difference is obtained in accordance with the signs, absolute values and amplitude ratio of two adjacent sample values. The sample values of said single frequency signal are taken at two points based on said digital phase locked loop clock signal corresponding to a phase difference of .pi./2 radians of said single frequency signal. A fast pull-in of the digital phase locked loop is realized by setting a value corresponding to the obtained phase difference into a dividing counter.