Patents by Inventor Kunio Kodama

Kunio Kodama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927225
    Abstract: A sliding spline shaft device of the present invention includes a male spline and a female spline that is fitted to the male spline in an axially slidable manner, and at least one of the splines has a surface processed layer. The surface processed layer includes an undercoat layer, an intermediate layer containing phosphate, and a topcoat layer containing solid lubricant, in this order. The undercoat layer contains iron nitride and/or iron carbide. Thus, the surface of a base material has high hardness. As a result, microscopic deformation of the sliding surface is reduced, and increase in a real contact area is suppressed, whereby stick-slip is prevented.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 12, 2024
    Assignees: NISSAN MOTOR CO., LTD., NIHON PARKERIZING CO., LTD.
    Inventors: Shigetoshi Kashiwabara, Kunio Katada, Shunsuke Hiraiwa, Akihumi Kawaguchi, Takeo Nishijima, Shinichi Suzuki, Yasuyuki Katsumada, Makoto Nakajima, Tokunori Kodama, Masato Ito, Aiki Iwasa
  • Patent number: 6344407
    Abstract: A semiconductor device manufacturing method comprises the steps of forming solder bumps on an underlying metal film of a semiconductor device, and placing the semiconductor device and the solder layer in a reduced pressure atmosphere containing formic acid to form the solder bumps. Accordingly, the solder bumps can be formed without flux generating voids in the solder layer. Furthermore, the cleaning required after the solder bumps are formed can be omitted.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: February 5, 2002
    Assignee: Fujitsu Limited
    Inventors: Hirohisa Matsuki, Fumihiko Taniguchi, Kunio Kodama, Eiji Watanabe, Masataka Mizukoshi, Hiroyuki Matsui
  • Patent number: 6218281
    Abstract: A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 &mgr;m or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: April 17, 2001
    Assignee: Fujitsu Limited
    Inventors: Eiji Watanabe, Hirohisa Matsuki, Kenichi Kado, Kenichi Nagashige, Masanori Onodera, Kunio Kodama, Hiroyuki Yoda, Joji Fujimori, Minoru Nakada, Yutaka Makino
  • Patent number: 5854558
    Abstract: A test board used for testing a semiconductor device provided with projection electrodes includes a main board and testing electrodes. The testing electrodes are provided on the main board, each projecting upwardly from the main board. When the semiconductor device is tested, the testing electrodes are electrically connected to the projection electrodes by insertion of the testing electrodes into the projection electrodes. The semiconductor device is mounted on the main board to test the semiconductor device through the testing electrodes.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: December 29, 1998
    Assignee: Fujitsu Limited
    Inventors: Toshiyuki Motooka, Syuichirou Takahashi, Tatsuharu Matsuda, Kunio Kodama, Jouji Fujimori
  • Patent number: 5831441
    Abstract: A test board used for testing a semiconductor device provided with projection electrodes includes a main board and testing electrodes. The testing electrodes are provided on the main board, each projecting upwardly from the main board. When the semiconductor device is tested, the testing electrodes are electrically connected to the projection electrodes by insertion of the testing electrodes into the projection electrodes. The semiconductor device is mounted on the main board to test the semiconductor device through the testing electrodes.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: November 3, 1998
    Assignee: Fujitsu Limited
    Inventors: Toshiyuki Motooka, Syuichirou Takahasi, Tatsuharu Matsuda, Kunio Kodama, Joji Fujimori, Shigeki Harada, Masataka Mizukoshi, Masashi Takenaka, Tatsuro Yamashita
  • Patent number: 4190555
    Abstract: A method is disclosed for preparing a catalyst system for polymerizing .alpha.-olefins. This method comprises admixing with at least an organoaluminum compound an activated titanium component which is prepared by first reacting a titanium compound of the general formula, TiX.sub.n (OR).sub.4-n (in which X is a halogen atom, R is an alkyl group or a phenyl group, and n is 2 to 4), with a metal of Group II or III of the Periodic Table and a halide of a metal of Group II or III of the Periodic Table in the presence of an aromatic compound, then treating the resulting reaction product with an oxygen-containing organic compound, and further treating with a tetrahalide of titanium, vanadium or both at a temperature of from -80.degree. C. to 80.degree. C., and finally aging at a temperature above 30.degree. C. for from 30 minutes to 24 hours.
    Type: Grant
    Filed: January 27, 1977
    Date of Patent: February 26, 1980
    Assignee: Mitsui Toatsu Chemicals, Incorporated
    Inventors: Yoshinori Takamura, Hakusei Hamada, Kiyoyuki Kitamura, Tetsuro Inada, Kunio Kodama, Katuyuki Usami