Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of other flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

Abstract: An electrically alterable non-volatile memory device is disclosed. In the device architecture of the memory device, control gates are formed, divided corresponding to the blocks and interconnected independently within each block, to further be connected to a metal gate line through block select MOS transistors which are formed on a semiconductor substrate between the blocks. All gate electrodes of the block select MOS transistors which are connected to the control gates interconnected as above within each block are further connected each other. These block select transistors can be controlled by applying erase block signals such as, EBS0, EBS1 and so on, to respective transistors. In addition, the control gates are further connected to a decoder such that some of these control gates may be selected through metal control gate lines.

Abstract: A semiconductor memory device in which MOS transistors are used. The device has diffusion lines and polysilicon lines formed on a semiconductor substrate, first and second insulating films covering the diffusion lines and the polysilicon lines, respectively. The diffusion lines extend at intervals and parallel with each other, and constitute bit lines of the memory device. The polysilicon lines extend at intervals, intersect the diffusion lines, and constitute word lines of the memory device. Metal wiring lines are formed on the second insulating film are each positioned over every other diffusion line in such a manner as to extend along the corresponding diffusion line, each metal wiring line being electrically connected to the corresponding diffusion line through a contact hole.

Abstract: A sense circuit of a semiconductor memory transistor includes a bit line connected to a memory cell which stores "1" or "0". The sense circuit includes a MOS transistor which has its gate connected to the bit line, its source connected to ground voltage and its drain connected to a supply voltage through a load MOS transistor. The sense circuit also includes a compensating circuit for compensating the voltage at the bit line when the ground voltage has fluctuated. For example, the compensating circuit includes a pull-up circuit for pulling up the voltage at the bit line when the ground voltage has shifted to the positive side and a pull-down circuit for pulling down the voltage at the bit line when the ground voltage has shifted to the negative side, thereby maintaining the relative voltage relationship between the voltage at the bit line and the ground voltage at a proper value.

Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.