Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a bandgap larger than a bandgap of the first nitride semiconductor layer, a gate electrode provided on the first nitride semiconductor layer, a first electrode provided on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a second electrode provided on the first nitride semiconductor layer, electrically connected to the first nitride semiconductor layer, and located between the first electrode and the second electrode, a first aluminum nitride layer that provided between the gate electrode and the second electrode, and provided on the second nitride semiconductor layer, and a second aluminum nitride layer provided on the first aluminum nitride layer. The first aluminum nitride layer is crystalline. The second aluminum nitride layer is non-crystalline.

Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes forming, on a substrate, a first conductivity type nitride semiconductor layer in which gallium nitride is contained, wherein the exposed face of the first conductivity type nitride semiconductor layer has a (0001) face, forming, on a substrate, a second conductivity type nitride semiconductor layer in which gallium nitride is contained, wherein the exposed face of the first conductivity type nitride semiconductor layer has a (000-1) face, and bonding the first conductivity type nitride semiconductor layer and the second conductivity type nitride semiconductor layer together by heating in a state where the first conductivity type nitride semiconductor layer faces and contacts the second conductivity type nitride semiconductor layer.

Abstract: According to one embodiment, a nitride semiconductor device including a first semiconductor layer and a second semiconductor layer is provided. The first semiconductor layer is provided on a base, and includes a nitride semiconductor. The first semiconductor layer includes a first region, and a second region which is provided on the first region, has a concentration of Si lower than a concentration of Si in the first region, and is thicker than the first region. The second semiconductor layer is provided on the first semiconductor layer.

Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.

Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.

Abstract: In one embodiment, a semiconductor device includes first and second semiconductor layers of a first conductivity type above a substrate via a first film, a first electrode above the second semiconductor layer, and a second electrode disposed on a side of the first electrode or an opposite side of the first electrode with respect to the second semiconductor layer. The device further includes a first pad layer connected to the first electrode, a second pad layer connected to the second electrode and including a first upper portion contacting the second electrode, a second upper portion disposed at a level between upper and lower portions of the substrate, and a third upper portion opposed to the lower portion of the substrate, and a third semiconductor layer of a second conductivity type between the second upper portion of the second pad layer and a lower portion of the first film.

Abstract: In one embodiment, a semiconductor device includes first and second semiconductor layers of a first conductivity type above a substrate via a first film, a first electrode above the second semiconductor layer, and a second electrode disposed on a side of the first electrode or an opposite side of the first electrode with respect to the second semiconductor layer. The device further includes a first pad layer connected to the first electrode, a second pad layer connected to the second electrode and including a first upper portion contacting the second electrode, a second upper portion disposed at a level between upper and lower portions of the substrate, and a third upper portion opposed to the lower portion of the substrate, and a third semiconductor layer of a second conductivity type between the second upper portion of the second pad layer and a lower portion of the first film.

Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.

Abstract: In a very high speed bipolar transistor, an n.sup.+ -type GaAs collector layer and an n-type GaAs collector layer are stacked in an intrinsic transistor region, and an i-type GaAs collector layer is formed around the n.sup.+ -type GaAs collector layer and the n-type GaAs collector layer. An n-type GaAs collector layer is formed on the n.sup.+ -type GaAs collector layer such that a part of the n-type GaAs collector layer extends on the i-type GaAs collector layer. A p-type GaAs external base layer is formed outside the n-type GaAs collector layer. A p.sup.+ -type Al.sub.x Ga.sub.l-x As base layer is formed on the n-type GaAs collector layer. An emitter layer is formed such that it is arranged only in the intrinsic transistor region on the p.sup.+ -type Al.sub.x Ga.sub.l-x As base layer and constitutes a heterojunction together with the base layer. Design trade-off between the cutoff frequency and maximum oscillation frequency of the transistor is eliminated.

Abstract: A compound semiconductor device wherein a contact to an n type Al.sub.x Ga.sub.1-x As layer comprises an In.sub.x Ga.sub.1-x As graded-composition layer, an In.sub.x Ga.sub.1-x As contact layer having a constant composition and a metal electrode layer, the In.sub.x Ga.sub.1-x As graded-composition layer is doped with an n type impurity which concentration is higher than a concentration of an impurity activated as n type, whereby, even when a thickness of the In.sub.x Ga.sub.1-x As graded-composition layer is made sufficiently small, a reduction in the carrier concentration of the thin graded-composition layer causes no increase of its resistance and a low-resistance contact is realized.