Patents by Inventor Kunizo Sahara

Kunizo Sahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5309011
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: May 3, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Patent number: 5191224
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: March 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Patent number: 5188280
    Abstract: A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: February 23, 1993
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 5090609
    Abstract: An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: February 25, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 5067007
    Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: November 19, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kanji Otsuka, Masao Kato, Takashi Kumagai, Mitsuo Usami, Shigeo Kuroda, Kunizo Sahara, Takeo Yamada, Seiji Miyamoto, Yuuji Shirai, Takayuki Okinaga, Kazutoshi Kubo, Hiroshi Tachi, Masayuki Kawashima
  • Patent number: 4764804
    Abstract: A semiconductor device having improved heat-dissipating characteristics employs a thin insulator film made of diamond, which has excellent thermal conductivity, as an insulator film which is formed on a chip immediately below a heat-dissipating bump electrode. Since the thin diamond film has excellent insulating properties and high thermal conductivity, it is possible to improve heat-dissipating characteristics of even a high-power semiconductor device such as a multichip module. In the case of, particularly, a multichip module, the insulation between a mother chip and a child chip can also be ensured by the presence of the thin diamond film.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: August 16, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Kunizo Sahara, Kanji Otsuka, Hisashi Ishida