Abstract: A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

Abstract: A shift register, a gate drive circuit, and a display panel are provided. The shift register includes an input sub-circuit configured to pre-charge a pull-up node using an input signal; an output sub-circuit configured to output a clock signal through an signal output terminal; a pull-down control sub-circuit configured to control a potential of a pull-down node using a power supply voltage signal; a first pull-down sub-circuit configured to pull down a potential of the pull-down node using a first preset voltage signal; and a first control sub-circuit configured to control the potential of the pull-up node using a second preset voltage signal in response to the potential of the pull-down node; a potential of the first preset voltage signal is lower than a potential of a non-operating level signal of the first pull-down sub-circuit, but higher than a potential of the second preset voltage signal.

Abstract: A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

Abstract: A shift register, a gate drive circuit, and a display panel are provided. The shift register includes an input sub-circuit configured to pre-charge a pull-up node using an input signal; an output sub-circuit configured to output a clock signal through an signal output terminal; a pull-down control sub-circuit configured to control a potential of a pull-down node using a power supply voltage signal; a first pull-down sub-circuit configured to pull down a potential of the pull-down node using a first preset voltage signal; and a first control sub-circuit configured to control the potential of the pull-up node using a second preset voltage signal in response to the potential of the pull-down node; a potential of the first preset voltage signal is lower than a potential of a non-operating level signal of the first pull-down sub-circuit, but higher than a potential of the second preset voltage signal.

Abstract: A semiconductor mixed material and manufacturing method thereof, a thin film transistor and an electronic device are provided. The semiconductor mixed material includes an inorganic semiconductor nanoparticle and an organic semiconductor material, and the inorganic semiconductor nanoparticle is dispersed in the organic semiconductor material. The embodiments of the present disclosure ensure both a high electron mobility and a high charge transfer rate by mixing the inorganic semiconductor nanoparticle with the organic semiconductor material.

Abstract: There is provided a thin film transistor including: a substrate; a gate electrode and a first electrode in a single layer on the substrate; an active layer above the first electrode, an orthographic projection of the active layer on the substrate at least partially covers an orthographic projection of the first electrode on the substrate; a first insulation layer covering the gate electrode, the first electrode, the active layer, a portion of the substrate exposed between the gate electrode and the active layer, and another portion of the substrate exposed between the gate electrode and the first electrode; and a second electrode above the first insulation layer, an orthographic projection of the second electrode on the substrate at least partially covers the orthographic projection of the active layer on the substrate, and the second electrode is connected to the active layer through a via-hole in the first insulation layer.

Abstract: There is provided a thin film transistor including: a substrate; a gate electrode and a first electrode in a single layer on the substrate; an active layer above the first electrode, an orthographic projection of the active layer on the substrate at least partially covers an orthographic projection of the first electrode on the substrate; a first insulation layer covering the gate electrode, the first electrode, the active layer, a portion of the substrate exposed between the gate electrode and the active layer, and another portion of the substrate exposed between the gate electrode and the first electrode; and a second electrode above the first insulation layer, an orthographic projection of the second electrode on the substrate at least partially covers the orthographic projection of the active layer on the substrate, and the second electrode is connected to the active layer through a via-hole in the first insulation layer.

Abstract: The present disclosure provides a pixel structure, a manufacturing method and a driving method thereof, and a display device. The pixel structure includes a plurality of pixel units, each pixel unit includes a first thin film transistor, a pixel electrode, and a common electrode, a drain of the first thin film transistor of the pixel unit is connected to the pixel electrode of the pixel unit. Each one of at least a portion of the plurality of pixel units further includes a second thin film transistor. A drain of the second thin film transistor of the pixel unit is connected to the common electrode of the pixel unit.