Patents by Inventor Kunlun Kenny JIANG

Kunlun Kenny JIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Loopback testing with phase alignment of a sampling clock at a test receiver apparatus
    Patent number: 8468398
    Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: June 18, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kunlun Kenny Jiang, Nancy Ngar Sze Chan
  • Pseudo full-rate sense amplifier flip-flop for high-speed receiver front-end
    Patent number: 8451027
    Abstract: An apparatus includes a first sensing circuit operative to drive a node with a first sample of an input signal during a first phase of a clock signal. The apparatus includes a second sensing circuit operative to drive the node with a second sample of the input signal during a second phase of the clock signal. An output signal on the node includes the first and second samples and has a bit rate that is N times the rate of the clock signal. N is an integer greater than one. In at least one embodiment of the apparatus, during the second phase of the clock signal, the first sensing circuit provides a high impedance to the node, and during the first phase of the clock signal, the second sensing circuit provides a high impedance to the node.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 28, 2013
    Assignee: ATI Technologies ULC
    Inventor: Kunlun Kenny Jiang
  • PSEUDO FULL-RATE SENSE AMPLIFIER FLIP-FLOP FOR HIGH-SPEED RECEIVER FRONT-END
    Publication number: 20120256672
    Abstract: An apparatus includes a first sensing circuit operative to drive a node with a first sample of an input signal during a first phase of a clock signal. The apparatus includes a second sensing circuit operative to drive the node with a second sample of the input signal during a second phase of the clock signal. An output signal on the node includes the first and second samples and has a bit rate that is N times the rate of the clock signal. N is an integer greater than one. In at least one embodiment of the apparatus, during the second phase of the clock signal, the first sensing circuit provides a high impedance to the node, and during the first phase of the clock signal, the second sensing circuit provides a high impedance to the node.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 11, 2012
    Inventor: Kunlun Kenny Jiang
  • LOOPBACK TESTING WITH PHASE ALIGNMENT OF A SAMPLING CLOCK AT A TEST RECEIVER APPARATUS
    Publication number: 20120192043
    Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Kunlun Kenny JIANG, Nancy Ngar Sze CHAN