Patents by Inventor Kunming Ho
Kunming Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11449660Abstract: A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary power/ground (PG) constraints based on power requirements of the element.Type: GrantFiled: March 10, 2021Date of Patent: September 20, 2022Assignee: Synopsys, Inc.Inventors: Jin Wu, Renu Mehra, Sabyasachi Das, Ben Mathew, Kunming Ho
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Patent number: 8656324Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.Type: GrantFiled: December 4, 2011Date of Patent: February 18, 2014Assignee: Cadence Design Systems, Inc.Inventors: Hung-Chun Li, Ming-Chyuan Chen, KunMing Ho
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Publication number: 20120079437Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.Type: ApplicationFiled: December 4, 2011Publication date: March 29, 2012Inventors: Hung-Chun Li, Ming-Chyuan Chen, KunMing Ho
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Patent number: 8074190Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.Type: GrantFiled: March 4, 2010Date of Patent: December 6, 2011Assignee: Cadence Design Systems, Inc.Inventors: Hung-Chun Li, Ming-Chyuan Chen, KunMing Ho
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Patent number: 7694242Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.Type: GrantFiled: December 11, 2006Date of Patent: April 6, 2010Assignee: Cadence Design Systems, Inc.Inventors: Hung-Chun Li, Ming-Chyuan Chen, KunMing Ho
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Patent number: 7079997Abstract: A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement.Type: GrantFiled: May 10, 2002Date of Patent: July 18, 2006Assignee: Novas Software, Inc.Inventors: Yu-Chin Hsu, Furshing Tsai, Yirng-An Chen, Kunming Ho, Tayung Liu, Chieh Changfan, Wells Woei-Tzy Jong
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Patent number: 7031899Abstract: A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.Type: GrantFiled: April 9, 2001Date of Patent: April 18, 2006Assignee: Novas Software, Inc.Inventors: Yu-Chin Hsu, Furshing Tsai, Tayung Liu, Bassam Tabbara, Kunming Ho, George Bakewell, Yirng-An Chen, Scott Sandler
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Publication number: 20020147576Abstract: A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.Type: ApplicationFiled: April 9, 2001Publication date: October 10, 2002Inventors: Yu-Chin Hsu, Furshing Tsai, Tayung Liu, Bassam Tabbara, Kunming Ho, George Bakewell