Abstract: The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.

Abstract: An internal voltage offset between a positive input and a negative input of a first operational amplifier is compensated. The negative input and the positive input of the first operational amplifier are coupled at the same voltage level. A comparison current generated at an output of the first operational amplifier has a sign that is representative of a sign of the internal voltage offset. The output of the first operational amplifier is biased to a threshold voltage using a current-to-voltage converter. A control voltage is generated from a sum of the threshold voltage and a voltage conversion of the comparison current. Compensation for the internal voltage offset between the positive and negative inputs of the first operational amplifier is made dependent on the control voltage.

Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.

Abstract: The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.

Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.

Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.

Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.

Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.

Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.

Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.

Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.

Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.

Abstract: An integrated circuit including at least one low-dropout voltage regulator (LDO) capable of delivering a regulated output voltage using a reference voltage (VREF), comprises means for generating a substitution voltage (VRMP) in the form of a ramp and control means capable of replacing the reference voltage (VREF) by the substitution voltage as long as the substitution voltage (VRMP) is lower than the reference voltage (VREF).

Abstract: A solution for increasing the switching speed of a bus driver circuit includes a pair of transistors controlled by a pair of control circuits. Pumping circuits are placed between the control electrodes of the transistors to speed up the conduction of one of the transistors immediately after the other is in an off state. An output interface for a differential bus is produced using two bus driver circuits, the control signals of one of the circuits being inverted relative to the other of the circuits.

Abstract: An integrated circuit includes a resistive circuit with reduced mismatch that includes a primary resistive network with several main resistances (Rp) each having the same theoretical main value. It also includes an auxiliary resistance (Rau) having an auxiliary theoretical resistive value equal to the product or to the quotient of the theoretical main resistive value by ?{square root over (2)}. All these resistances are connected together so as to attribute a theoretical overall resistive value to the primary resistive network equal to the theoretical auxiliary resistive value.

Abstract: A solution for increasing the switching speed of a bus driver circuit includes a pair of transistors controlled by a pair of control circuits. Pumping circuits are placed between the control electrodes of the transistors to speed up the conduction of one of the transistors immediately after the other is in an off state. An output interface for a differential bus is produced using two bus driver circuits, the control signals of one of the circuits being inverted relative to the other of the circuits.

Abstract: An integrated circuit includes a resistive circuit with reduced mismatch that includes a primary resistive network with several main resistances (Rp) each having the same theoretical main value. It also includes an auxiliary resistance (Rau) having an auxiliary theoretical resistive value equal to the product or to the quotient of the theoretical main resistive value by ?{square root over (2)}. All these resistances are connected together so as to attribute a theoretical overall resistive value to the primary resistive network equal to the theoretical auxiliary resistive value.

Abstract: An integrated circuit including at least one low-dropout voltage regulator (LDO) capable of delivering a regulated output voltage using a reference voltage (VREF), comprises means for generating a substitution voltage (VRMP) in the form of a ramp and control means capable of replacing the reference voltage (VREF) by the substitution voltage as long as the said substitution voltage (VRMP) is lower than the said reference voltage (VREF).

Abstract: A low noise differential amplifier structure comprising a first amplifier provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. A second amplifier is provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. The structure is characterized in that it comprises: at least a first trimming capacitor having a first electrode connected to the first electrode of the first Miller capacitor; at least a second trimming capacitor having a first electrode connected to the first electrode of the second Miller capacitor; and a cascode stage having an input receiving the output common mode voltage and an output connected to the second electrode of the first and second trimming capacitors.

Abstract: A low noise differential amplifier structure comprising a first amplifier provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. A second amplifier is provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. The structure is characterized in that it comprises: at least a first trimming capacitor having a first electrode connected to the first electrode of the first Miller capacitor; at least a second trimming capacitor having a first electrode connected to the first electrode of the second Miller capacitor; and a cascode stage having an input receiving the output common mode voltage and an output connected to the second electrode of the first and second trimming capacitors.