Abstract: A fail-safe multiprocessor system comprises processors connected through a switching unit which forms a data transfer channel between the processors. This switching unit comprises mechanical switches that can selectively connect peripheral units (e.g., display units) with one of the processors. The transfer device constitutes, from the standpoint of each of the connected processors, a normal peripheral unit. The switches are set either manually or automatically under program control by each of the processors. In the case of an error or failure, the data processing system is reconfigured such that the high priority tasks together with their associated peripheral units are transferred from the failed processor to a processor which is still intact.

Abstract: Storage hierarchy comprising a main store with user and program data (L), a control store with micro code (C), and a processor buffer store which is commonly used for both data types (L & C). With no restrictions imposed, allocation of buffer space for L and C type data is self-adapting, since the address and replacement array are used jointly for both types of data.Alternatively, to reserve at least a minimum amount of buffer space for L and C type blocks, respectively, one or two space limit values may be defined and adhered to each time buffer block space is allocated anew. Thus the buffer space may be shared by the two types of data either in a fully overlapping (no space limit values), in a partly overlapping (two space limit values) or in a non-overlapping manner (one space limit value).