Patents by Inventor Kun Young Lee
Kun Young Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953211Abstract: A method and an apparatus for real-time analysis of the district heating network is disclosed. According to an embodiment of the present disclosure, a method for analyzing a district heating network including pipes and fluids inside the pipes includes receiving, by a processor, pipe data representing a structure of the pipes; receiving, by the processor, input data on at least one of the physical state of the district heating network and the flow of fluids; calculating, by the processor, data for at least one of the physical state of the district heating network or the flow of fluids using the pipe data and the input data.Type: GrantFiled: January 20, 2023Date of Patent: April 9, 2024Assignee: GS Power Co. Ltd.Inventors: Yuan Hu Li, Chang Yeol Yoon, Ki Song Lee, Kun Young Lee, Tae Gon Kim
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Patent number: 11930642Abstract: A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.Type: GrantFiled: December 6, 2022Date of Patent: March 12, 2024Assignee: SK hynix Inc.Inventors: Kun Young Lee, Changhan Kim, Sung Hyun Yoon
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Patent number: 11903185Abstract: Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.Type: GrantFiled: December 22, 2021Date of Patent: February 13, 2024Assignee: SK hynix Inc.Inventors: Kun-Young Lee, Sun-Young Kim
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Publication number: 20230380160Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device may include a stack structure including a plurality of conductive layers, a hole formed in the stack structure, a memory layer allowing a first part and a second part of the hole to be spaced apart from each other in the hole, and a first channel layer disposed in the first part of the hole and a second channel layer disposed in the second part of the hole.Type: ApplicationFiled: October 25, 2022Publication date: November 23, 2023Applicant: SK hynix Inc.Inventor: Kun Young LEE
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Patent number: 11812612Abstract: A semiconductor device includes a stacked structure with conductive layers and insulating layers that are stacked alternately with each other, an insulating pillar passing through the stacked structure, a first channel pattern surrounding a sidewall of the insulating pillar, a second channel pattern surrounding the sidewall of the insulating pillar, a first insulator formed between the first channel pattern and the second channel pattern, and a memory layer surrounding the first channel pattern, the second channel pattern, and the first insulator, the memory layer with a first opening located that is between the first channel pattern and the second channel pattern.Type: GrantFiled: January 12, 2021Date of Patent: November 7, 2023Assignee: SK hynix Inc.Inventors: Kun Young Lee, Dong Hyoub Kim
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Patent number: 11805656Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, a first dielectric layer surrounding a sidewall of the ferroelectric layer, and sacrificial patterns interposed between the first dielectric layer and the insulating layers and including a material with a higher dielectric constant than the first dielectric layer.Type: GrantFiled: May 19, 2022Date of Patent: October 31, 2023Assignee: SK hynix Inc.Inventors: Kun Young Lee, Changhan Kim, Sung Hyun Yoon
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Publication number: 20230320086Abstract: A semiconductor memory device includes: a first gate stack structure including first interlayer insulating layers and first conductive layers, which are alternately stacked in a vertical direction; a dummy vertical channel penetrating the first gate stack structure; lower vertical channels penetrating the first gate stack structure at both sides of the dummy vertical channel; a second gate stack structure including second interlayer insulating layers and second conductive layers, which are alternately stacked in the vertical direction on the first gate stack structure; a first select line isolation structure partially penetrating the second gate stack structure; upper vertical channels connected to the lower vertical channels while penetrating the second gate stack structure; and a second select line isolation structure overlapping with the dummy vertical channel in the vertical direction, the second select line isolation structure penetrating a portion of the second gate stack structure.Type: ApplicationFiled: October 3, 2022Publication date: October 5, 2023Applicant: SK hynix Inc.Inventors: Kun Young LEE, Sang Soo KIM, Sang Wan JIN
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Publication number: 20230301096Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of conductive patterns and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; a plurality of channel structures extending in a first direction substantially perpendicular to the substrate to penetrate the stack structure; at least one first slit extending in a second direction substantially horizontal to the substrate while penetrating conductive patterns for select lines among the plurality of conductive patterns; a second slit extending in the second direction while penetrating the conductive patterns for select lines; and a plurality of support structures disposed on a bottom of the second slit, the plurality of support structures penetrating conductive patterns for word lines among the plurality of conductive patterns.Type: ApplicationFiled: September 13, 2022Publication date: September 21, 2023Applicant: SK hynix Inc.Inventors: Kun Young LEE, Sang Soo KIM, Nam Kuk KIM, Sang Wan JIN
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Publication number: 20230260928Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.Type: ApplicationFiled: April 20, 2023Publication date: August 17, 2023Applicant: SK hynix Inc.Inventors: Kun Young LEE, Tae Kyung KIM
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Publication number: 20230235897Abstract: A method and an apparatus for real-time analysis of the district heating network is disclosed. According to an embodiment of the present disclosure, a method for analyzing a district heating network including pipes and fluids inside the pipes includes receiving, by a processor, pipe data representing a structure of the pipes; receiving, by the processor, input data on at least one of the physical state of the district heating network and the flow of fluids; calculating, by the processor, data for at least one of the physical state of the district heating network or the flow of fluids using the pipe data and the input data.Type: ApplicationFiled: January 20, 2023Publication date: July 27, 2023Inventors: Yuan Hu LI, Chang Yeol YOON, Ki Song LEE, Kun Young LEE, Tae Gon KIM
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Patent number: 11705402Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.Type: GrantFiled: April 7, 2022Date of Patent: July 18, 2023Assignee: SK hynix Inc.Inventors: Kun Young Lee, Tae Kyung Kim
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Patent number: 11664326Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.Type: GrantFiled: April 7, 2022Date of Patent: May 30, 2023Assignee: SK hynix Inc.Inventors: Kun Young Lee, Tae Kyung Kim
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Patent number: 11659715Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.Type: GrantFiled: December 23, 2021Date of Patent: May 23, 2023Assignee: SK hynix Inc.Inventors: Kun Young Lee, Sun Young Kim, Jae Gil Lee
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Publication number: 20230109965Abstract: A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.Type: ApplicationFiled: December 6, 2022Publication date: April 13, 2023Applicant: SK hynix Inc.Inventors: Kun Young LEE, Changhan KIM, Sung Hyun YOON
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Patent number: 11563032Abstract: A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.Type: GrantFiled: January 18, 2021Date of Patent: January 24, 2023Assignee: SK hynix Inc.Inventors: Kun Young Lee, Changhan Kim, Sung Hyun Yoon
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Patent number: 11488979Abstract: A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer.Type: GrantFiled: October 20, 2020Date of Patent: November 1, 2022Assignee: SK hynix Inc.Inventors: Jae Gil Lee, Kun Young Lee, Hyangkeun Yoo
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Publication number: 20220344346Abstract: A method for fabricating a semiconductor device includes: forming a mold stack layer including a mold layer and a supporter layer over a substrate; forming opening by etching the mold stack layer; selectively forming a supporter reinforcement layer on an exposed surface of the supporter layer which is positioned in the opening; forming a bottom electrode in the opening in which the supporter reinforcement layer is formed; and forming a supporter opening by etching a portion of the supporter layer to form a supporter that supports an outer wall of the bottom electrode.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventors: Kun Young LEE, Seo Hyun KIM
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Publication number: 20220278131Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, a first dielectric layer surrounding a sidewall of the ferroelectric layer, and sacrificial patterns interposed between the first dielectric layer and the insulating layers and including a material with a higher dielectric constant than the first dielectric layer.Type: ApplicationFiled: May 19, 2022Publication date: September 1, 2022Applicant: SK hynix Inc.Inventors: Kun Young LEE, Changhan KIM, Sung Hyun YOON
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Patent number: 11411005Abstract: A method for fabricating a semiconductor device includes: forming a mold stack layer including a mold layer and a supporter layer over a substrate; forming opening by etching the mold stack layer; selectively forming a supporter reinforcement layer on an exposed surface of the supporter layer which is positioned in the opening; forming a bottom electrode in the opening in which the supporter reinforcement layer is formed; and forming a supporter opening by etching a portion of the supporter layer to form a supporter that supports an outer wall of the bottom electrode.Type: GrantFiled: July 22, 2020Date of Patent: August 9, 2022Assignee: SK hynix Inc.Inventors: Kun Young Lee, Seo Hyun Kim
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Publication number: 20220230966Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Applicant: SK hynix Inc.Inventors: Kun Young LEE, Tae Kyung KIM