Abstract: A lidar device (100), including: a transmitter module (120), a receiver monolithic module (150), and a coordination circuit module (110) connected to the transmitter module (120) and the receiver monolithic module (150), wherein components of the transmitter module (120), the receiver monolithic module (150) and the coordination circuit module (110) are all solid-state electronic components or micro-electro-mechanical components.

Abstract: A laser ranging receiver device, which is provided on a single chip and comprises a plurality of photoelectric conversion modules and a plurality of time-to-digital converters; clock generation and distribution modules; and a digital control circuit, the digital control circuit comprising a data storage module, a digital signal processing module, a timing control module, and a chip interface circuit.

Abstract: A lidar device (100), including: a transmitter module (120), a receiver monolithic module (150), and a coordination circuit module (110) connected to the transmitter module (120) and the receiver monolithic module (150), wherein components of the transmitter module (120), the receiver monolithic module (150) and the coordination circuit module (110) are all solid-state electronic components or micro-electro-mechanical components.

Abstract: An example optical receiver may have an optical receiver front-end, four slicers, and a logic block. The optical receiver front-end may include a transimpedance amplifier to convert a photodiode output signal to a voltage signal. Three of the slicers may be data slicers, and one of the slicers may be an edge slicer. The slicers may each: shift the voltage signal based on an offset voltage set for the respective slicer, determine whether the shifted voltage signal is greater than a threshold value and generate a number of comparison signals based on the determining, and generate multiple digital signals by demuxing the comparison signals. The logic block may perform PAM-4 to binary decoding based on the data signals output by the data slicers and clock-and-data-recovery based on the digital signals output by the edge slicer.

Abstract: In one example, a device includes a photodetector to generate an electrical signal in response to an optical signal and a transimpedance amplifier unit to receive the electrical signal. In one example, the transimpedance amplifier unit may include a first inverter unit, a second inverter unit coupled to the first inverter unit, and a third inverter unit coupled to the second inverter unit. In one example the third inverter unit may include a feedback resistor and a first n-type transistor in parallel to the feedback resistor, where the first n-type transistor is to provide a variable gain of the third inverter unit.

Abstract: An example optical receiver may have an optical receiver front-end, four slicers, and a logic block. The optical receiver front-end may include a transimpedance amplifier to convert a photodiode output signal to a voltage signal. Three of the slicers may be data slicers, and one of the slicers may be an edge slicer. The slicers may each: shift the voltage signal based on an offset voltage set for the respective slicer, determine whether the shifted voltage signal is greater than a threshold value and generate a number of comparison signals based on the determining, and generate multiple digital signals by demuxing the comparison signals. The logic block may perform PAM-4 to binary decoding based on the data signals output by the data slicers and clock-and-data-recovery based on the digital signals output by the edge slicer.

Abstract: In one example, a device includes a photodetector to generate an electrical signal in response to an optical signal and a transimpedance amplifier unit to receive the electrical signal. In one example, the transimpedance amplifier unit may include a first inverter unit, a second inverter unit coupled to the first inverter unit, and a third inverter unit coupled to the second inverter unit. In one example the third inverter unit may include a feedback resistor and a first n-type transistor in parallel to the feedback resistor, where the first n-type transistor is to provide a variable gain of the third inverter unit.

Abstract: In one example, an apparatus includes an offset tunable edge slicer having an input to receive a pulse amplitude modulation signal. The offset tunable edge slicer also has a plurality of possible offset settings corresponding to a plurality of different reference voltages of the offset tunable edge slicer. A multiplexer has an output coupled to the input of the offset tunable edge slicer and an input to receive a control signal that selects one of the plurality of possible offset settings for the offset tunable edge slicer. A phase detector has an input coupled to an output of the offset tunable edge slicer.

Abstract: In one example, an apparatus includes an offset tunable edge slicer having an input to receive a pulse amplitude modulation signal. The offset tunable edge slicer also has a plurality of possible offset settings corresponding to a plurality of different reference voltages of the offset tunable edge slicer. A multiplexer has an output coupled to the input of the offset tunable edge slicer and an input to receive a control signal that selects one of the plurality of possible offset settings for the offset tunable edge slicer. A phase detector has an input coupled to an output of the offset tunable edge slicer.