Patents by Inventor KUO-AN HSIEH
KUO-AN HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145596Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
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Publication number: 20240120203Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.Type: ApplicationFiled: March 8, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
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Patent number: 11926017Abstract: A cleaning process monitoring system, comprising: a cleaning container comprising an inlet for receiving a cleaning solution and an outlet for draining a waste solution; a particle detector coupled to the outlet and configured to measure a plurality of particle parameters associated with the waste solution so as to provide a real-time monitoring of the cleaning process; a pump coupled to the cleaning container and configured to provide suction force to draw solution through the cleaning system; a controller coupled to the pump and the particle detector and configured to receive the plurality of particle parameters from the particle detector and to provide control to the cleaning system; and a host computer coupled to the controller and configured to provide at least one control parameter to the controller.Type: GrantFiled: May 5, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Charlie Wang, Yu-Ping Tseng, Y. J. Chen, Wai-Ming Yeung, Chien-Shen Chen, Danny Kuo, Yu-Hsuan Hsieh, Hsuan Lo
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Publication number: 20230369325Abstract: In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Yang-Cheng Wu, Yun-Hua Chen, Wen-Kuo Hsieh, Huan-Just Lin
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Patent number: 11798943Abstract: In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.Type: GrantFiled: June 4, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yang-Cheng Wu, Yun-Hua Chen, Wen-Kuo Hsieh, Huan-Just Lin
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Publication number: 20220262792Abstract: In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.Type: ApplicationFiled: June 4, 2021Publication date: August 18, 2022Inventors: Yang-Cheng Wu, Yun-Hua Chen, Wen-Kuo Hsieh, Huan-Just Lin
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Patent number: 11246238Abstract: A heat conductive device includes a heat conductive unit, a wick structure, a heat transferring unit, and a heat conductive fluid. The heat conductive unit has a closed chamber. The wick structure is disposed on the inner side surface of the closed chamber. The heat transferring unit includes a plurality of heat conductive elements agglomerated into islands and separated from each other. The heat conductive elements are disposed on the partial surface of the wick structure. The heat conductive fluid is disposed in the closed chamber. An electronic device including the heat conductive device is also provided. The heat conductive device has a good heat conductive efficiency.Type: GrantFiled: May 29, 2020Date of Patent: February 8, 2022Assignees: SULFURSCIENCE TECHNOLOGY CO., LTD., MING CHI UNIVERSITY OF TECHNOLOGYInventors: Zhen-Yu Juang, Sung-Yen Wei, Chia-Chin Cheng, Chien-Kuo Hsieh
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Patent number: 11018021Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.Type: GrantFiled: July 8, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Kuo Hsieh, Tsung-Hung Chu, Ming-Chung Liang
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Patent number: 10510584Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: GrantFiled: July 1, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Publication number: 20190333777Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Inventors: Wen-Kuo Hsieh, Tsung-Hung Chu, Ming-Chung Liang
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Publication number: 20190326164Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Patent number: 10347505Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.Type: GrantFiled: April 4, 2016Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Kuo Hsieh, Tsung-Hung Chu, Ming-Chung Liang
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Patent number: 10340178Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: GrantFiled: November 26, 2018Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Publication number: 20190096752Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Patent number: 10141220Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: GrantFiled: September 1, 2017Date of Patent: November 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Patent number: 10118333Abstract: A film application apparatus includes a first base configured to couple a film material and a second base rotatably coupled to the first base. The first base defines an opening and two through holes on opposite side of the first base, the through holes communicate with the opening. The second base defines a receiving chamber and the receiving chamber is configured for accommodating a work piece. The film application apparatus further includes a pressing component inserted through the first base, the pressing component penetrating through the opening from the two through holes for pressing the film material against to a face of the work piece.Type: GrantFiled: August 28, 2015Date of Patent: November 6, 2018Assignees: SHENZHENSHI YUZHAN PRECISION TECHNOLOGY, Cloud Network Technology Singapore Pte. Ltd.Inventors: Xin-Jian Zhang, Kuo-An Hsieh, Xian-Lin Yang, Xin Hou, Ke-Feng Zhu
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Publication number: 20170365508Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: ApplicationFiled: September 1, 2017Publication date: December 21, 2017Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Patent number: 9754818Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: GrantFiled: August 2, 2016Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
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Patent number: 9728445Abstract: In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a dielectric layer sequentially formed thereon. The method also includes etching the dielectric layer to form a first via hole of a first size and a second via hole of a second size within the dielectric layer by a plasma generated from an etch gas, until both the first via hole and the second via hole are reaching the etch stop layer. The etch gas includes CH2F2 and an auxiliary gas of N2 or O2.Type: GrantFiled: January 22, 2014Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Kuo Hsieh, Ming-Chung Liang
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Publication number: 20170200636Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.Type: ApplicationFiled: August 2, 2016Publication date: July 13, 2017Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng