Patents by Inventor Kuo-Chang Kau
Kuo-Chang Kau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921434Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.Type: GrantFiled: December 15, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11740563Abstract: A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.Type: GrantFiled: February 22, 2022Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20230124211Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20220328304Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.Type: ApplicationFiled: July 8, 2021Publication date: October 13, 2022Inventors: Kuo-Chang Kau, Wen-Yun Wang, Chia-Chu Liu, Hua-Tai Lin
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Publication number: 20220179326Abstract: A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11256179Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: GrantFiled: October 22, 2019Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 10825684Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.Type: GrantFiled: January 6, 2017Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Hao Chang, Chien-Chih Chen, Kuo-Chang Kau, Jeng-Horng Chen, Pi-Yeh Chia, Chi-Ren Chen, Ying-Chih Lin
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Patent number: 10685846Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.Type: GrantFiled: May 16, 2014Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chin Chien, Jui-Ching Wu, Shu-Hao Chang, Shang-Chieh Chien, Jen-Yang Chung, Kuo-Chang Kau, Jeng-Horng Chen
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Publication number: 20200050118Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 10514610Abstract: Disclosed is an apparatus for lithography patterning. The apparatus includes a substrate stage configured to hold a substrate coated with a deposition enhancement layer (DEL), a radiation source for generating a patterned radiation towards a surface of the DEL, and a supply pipe for flowing an organic gas near the surface of the DEL, wherein elements of the organic gas polymerize upon the patterned radiation, thereby forming a resist pattern over the DEL.Type: GrantFiled: July 9, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao Chang, Kuo-Chang Kau, Kevin Huang, Jeng-Horng Chen
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Patent number: 10459352Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: GrantFiled: August 31, 2015Date of Patent: October 29, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20180314167Abstract: Disclosed is an apparatus for lithography patterning. The apparatus includes a substrate stage configured to hold a substrate coated with a deposition enhancement layer (DEL), a radiation source for generating a patterned radiation towards a surface of the DEL, and a supply pipe for flowing an organic gas near the surface of the DEL, wherein elements of the organic gas polymerize upon the patterned radiation, thereby forming a resist pattern over the DEL.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Inventors: Shu-Hao Chang, Kuo-Chang Kau, Kevin Huang, Jeng-Horng Chen
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Patent number: 10018920Abstract: Disclosed is a method for lithography patterning. The method includes providing a substrate, forming a deposition enhancement layer (DEL) over the substrate, and flowing an organic gas near a surface of the DEL. During the flowing of the organic gas, the method further includes irradiating the DEL and the organic gas with a patterned radiation. Elements of the organic gas polymerize upon the patterned radiation, thereby forming a resist pattern over the DEL. The method further includes etching the DEL with the resist pattern as an etch mask, thereby forming a patterned DEL.Type: GrantFiled: March 4, 2016Date of Patent: July 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao Chang, Kuo-Chang Kau, Kevin Huang, Jeng-Horng Chen
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Publication number: 20170271150Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.Type: ApplicationFiled: January 6, 2017Publication date: September 21, 2017Inventors: Shu-Hao CHANG, Chien-Chih CHEN, Kuo-Chang KAU, Jeng-Horng CHEN, Pi-Yeh CHIA, Chi-Ren CHEN, Ying-Chih LIN
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Publication number: 20170256418Abstract: Disclosed is a method for lithography patterning. The method includes providing a substrate, forming a deposition enhancement layer (DEL) over the substrate, and flowing an organic gas near a surface of the DEL. During the flowing of the organic gas, the method further includes irradiating the DEL and the organic gas with a patterned radiation. Elements of the organic gas polymerize upon the patterned radiation, thereby forming a resist pattern over the DEL. The method further includes etching the DEL with the resist pattern as an etch mask, thereby forming a patterned DEL.Type: ApplicationFiled: March 4, 2016Publication date: September 7, 2017Inventors: SHU-HAO CHANG, KUO-CHANG KAU, KEVIN HUANG, JENG-HORNG CHEN
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Patent number: 9607833Abstract: The method includes performing a photolithography process which includes using a photomask to pattern a radiation beam. The photolithography process also includes exposing a target substrate to the patterned radiation beam. During the exposing of the target surface, there is a real-time monitoring for particles incident or approximate the photomask.Type: GrantFiled: January 30, 2015Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Hsiang-Yu Chou, Kuo-Chang Kau, Shun-Der Wu, Chia-Chen Chen, Jeng-Horng Chen
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Publication number: 20170060005Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 9570302Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a radiation-removable-material (RRM) layer over a substrate and removing a first portion of the RRM layer in a first region of the substrate by exposing the first portion of the RRM layer to a radiation beam. A second portion of the RRM layer in a second region of the substrate remains after the removing of the first portion of the RRM layer in the first region. The method also includes forming a selective-forming-layer (SFL) over the second portion of the RRM layer in the second region of the substrate and forming a material layer over the first region of the substrate.Type: GrantFiled: February 10, 2016Date of Patent: February 14, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Hao Chang, Kuo-Chang Kau, Kevin Huang, Jeng-Horng Chen
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Publication number: 20160225610Abstract: The method includes performing a photolithography process which includes using a photomask to pattern a radiation beam. The photolithography process also includes exposing a target substrate to the patterned radiation beam. During the exposing of the target surface, there is a real-time monitoring for particles incident or approximate the photomask.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: Shang-Chieh Chien, Shu-Hao Chang, Hsiang-Yu Chou, Kuo-Chang Kau, Shun-Der Wu, Chia-Chen Chen, Jeng-Horng Chen
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Publication number: 20150332922Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.Type: ApplicationFiled: May 16, 2014Publication date: November 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chin Chien, Jui-Ching Wu, Shu-Hao Chang, Shang-Chieh Chien, Jen-Yang Chaung, Kuo-Chang Kau, Jeng-Horng Chen